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Design and Implementation of Multiple-Output CMOS Voltage Level Shifter

  • S. SwaroopEmail author
  • K. S. Ravindra
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 614)

Abstract

Different parts such as digital, analog, passive components are manufactured on a single chip in system on chip (SoC) design and require different voltages to achieve optimum performance. The voltage level shifter (LS) is a device that changes over level of voltage to other level of voltage. Different circuit squares working at various supply voltages are interfaced with voltage LS. The SoC voltage LS is used at the edge of various islands of voltage. Single-output and multiple-output CMOS LS are implemented. The proposed voltage LS converts low voltage input to high voltage output with higher speed and lower power consumption. The design of the architecture is implemented using CMOS technique. Multi-threshold voltage CMOS technology is used to decrease power and delay when designing the voltage LS. To minimize delay, device with low-threshold voltage is used. Using high-threshold voltage devices, power dissipation can be reduced. In 45 nm technology, the design was implemented. Comparison is made of the power dissipation and propagation delay.

Keywords

Very large scale integrated circuit (VLSI) Complementary metal oxide semiconductor (CMOS) Level shifter (LS) Low voltage transistors (LVT) High voltage transistors (HVT) Standard voltage transistor (SVT) 

References

  1. 1.
    Nisha RM (2016) High speed level shifter design for low power application using 45 nm technology. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(9):1103–1107Google Scholar
  2. 2.
    Wang W-T, Ker M-D, Chiang M-C, Chen C-H (2001) Level shifters for high-speed 1–3.3V interfaces in a 0.13 µm Cu-interconnection/low-k CMOS technology. In: International symposium on VLSI technology, systems, and applications, pp 307–310, IEEEGoogle Scholar
  3. 3.
    Han S-M, Nam W-J, Park H-S, Kim S-J, Park K-C, Han M-K (2006) A low power wide range CMOS poly-Si level shifter for active matrix display. In: Proceedings of Asian symposium on information display (ASID), New DelhiGoogle Scholar
  4. 4.
    Kumar M, Arya SK, Pandey S (2010) Level shifter design for low power applications. Int J Comput Sci Inf Technol (IJCSIT) 2(5)CrossRefGoogle Scholar
  5. 5.
    Gupta Shweta, Kumar Manoj (2013) CMOS voltage level-up shifter—a review. Int J Adv Eng Sci 3:71–74Google Scholar
  6. 6.
    Thakur S, Mehra R (2013) CMOS design and single supply level shifter using 90 nm technology. In: Conference on advances in communication and control systems, vol 8, No 7Google Scholar
  7. 7.
    Liu W, Salman E, Sitik C, Taskin B (2015) Enhanced level shifter for multi-voltage operation. In: International symposium on circuits and systems (ISCAS), pp 1442–1445, IEEEGoogle Scholar
  8. 8.
    Gosatwar P, Ghodeswar U (2016) Design of voltage level shifter for multi-supply voltage design. In: International conference on communication and signal processing (ICCSP), pp 0853–0857, IEEEGoogle Scholar
  9. 9.
    Badal MT, Reaz MM, Farayez A, Ramli SA, Kamal N (2017) Design of a low-power CMOS level shifter for low-delay SoCs in silterra 0.13 μm CMOS process. J Eng Sci Technol Rev 10(4):10–15CrossRefGoogle Scholar
  10. 10.
    Rana V, Sinha R (2018) Stress relaxed multiple output high-voltage level shifter. IEEE Trans Circ Syst II Express Briefs 65 2:176–180Google Scholar
  11. 11.
    Gupta HS, Kirkire S, Bhati S, Chaurasia RS, Mehta S, Choudhary AR, Patel D, Vaghela J (2015) Bipolar voltage level shifter. In: International symposium on VLSI design and test (VDAT), pp 1–5, IEEEGoogle Scholar
  12. 12.
    García JC, Juan A, Nooshabadi S (2017) Single supply CMOS up level shifter for dual voltage system. In: International symposium on circuits and systems (ISCAS), pp 1–4, IEEEGoogle Scholar
  13. 13.
    Cai J, Halak B, Rossi D (2016) Analysis of BTI aging of level shifters. In: International symposium on on-line testing and robust system design (IOLTS), pp 17–18, IEEEGoogle Scholar
  14. 14.
    Haas M, Ortmanns M (2016) A floating high-voltage LS with high area efficiency for biomedical implants. In: Conference on Ph.D. research in microelectronics and electronics (PRIME), pp 1–4, IEEEGoogle Scholar
  15. 15.
    Gak J, Miguez M, Arnaud A, Mandolesi PS (2017) Blind range level shifters from 0 to 18 V. In: Latin American symposium on circuits and systems (LASCAS), pp 1–4, IEEEGoogle Scholar
  16. 16.
    Pashmineh S, Killat D (2015) Design of high-voltage level shifters based on stacked standard transistors for a wide range of supply voltages. In: Symposium on integrated circuits and systems design (SBCCI), pp 1–6, IEEEGoogle Scholar
  17. 17.
    Patkar K, Akashe S (2016) Design of level shifter for low power applications. In: Symposium on colossal data analysis and networking (CDAN), pp 1–4, IEEEGoogle Scholar
  18. 18.
    Kim TTH (2018) An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65 nm CMOS. IEEE Trans Circ Syst II Expr Briefs 65(5):607–611Google Scholar
  19. 19.
    Thomas S, Varghese GT (2017) Design of optimum power, delay efficient level shifter for biomedical applications. In: International conference on intelligent computing, instrumentation and control technologies (ICICICT), pp 219–222, IEEEGoogle Scholar
  20. 20.
    Frenila JB, Paglinawan AC (2017) Design of a 1.8 V-input 6.5 V-output digital level shifter for trimming application. In: International conference on humanoid, nanotechnology, information technology, communication and control, environment and management (HNICEM), pp 1–6, IEEEGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.Department of ECENMAM Institute of TechnologyNitteIndia

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