UVM-Based CAN IP Verification
Abstract
In this paper, a verification testbench-based UVM is established for a CAN IP. To adapt to some features of the CAN IP and improve the efficiency of the verification, appropriate strategies and methods are implemented, such as the constraint random stimulus, register model with indirect indexed registers, the coverage-driven strategy, and a reference model for automatic comparison. It’s proved that UVM-based verification testbench can make the process of verification clearer and more efficient. During the verification, we find some problems of the CAN IP. After solving them, we take regression test and all these problems are solved. Finally, we collect the function coverage and code coverage as the evaluation of the verification, and two of them could prove that the CAN IP could be used for FPGA firmware design.
Keywords
UVM verification CAN IP Constraint random stimulus Coverage-driven strategy Regression test FPGA firmware designReferences
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