A New Compact Multilevel Inverter Design with Less Power Electronics Component

  • Siddharth PachporEmail author
  • Subhankar Dutta
  • M. Jagabar Sathik
  • Mudit Babel
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 989)


Nowadays, multilevel inverter with reduced switch count is more attractive among the researchers due to the unsuitability of the conventional multilevel inverter where the installation space is constrained. Two different algorithms have been proposed for determining the magnitude of DC voltage sources. In this project, a compact version of multilevel inverter design is suggested with reduced and limited power electronic components, which are compared with conventional and recent multilevel inverter topology in terms of a number of levels, auxiliary diode, gate driver circuits, and blocking voltage of switches. Simulation software such as MATLAB/Simulink and laboratory workbench-based experimental test has been conducted. Finally, the comparison between the simulation output and experimental is discussed to prove the superiority of suggested topology.


Multilevel inverter Blocking voltages DC voltage sources Switches Gate driver circuits 



We also take the opportunity to express a deep sense of gratitude and deep regards to our program guide Dr. Arun Noyal Doss, M.E. Ph.D and Dr Prabodh Pachpor, Ph.D for their able guidance and support. They not only motivated throughout the project but also additionally provided with constructive criticism.


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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  • Siddharth Pachpor
    • 1
    Email author
  • Subhankar Dutta
    • 1
  • M. Jagabar Sathik
    • 1
  • Mudit Babel
    • 2
  1. 1.Department of Electrical and Electronics EngineeringSRM Institute of Science and TechnologyChennaiIndia
  2. 2.Department of Electronics and Telecommunication EngineeringRajiv Gandhi College of Engineering and ResearchNagpurIndia

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