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Compact and Secure S-Box Implementations of AES—A Review

  • Amrik SinghEmail author
  • Ajay Prasad
  • Yoginder Talwar
Conference paper
  • 220 Downloads
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 141)

Abstract

S-Box is implemented normally by using lookup tables (LUT) in which 256 predefined values of S-Box and the same numbers for Inverse S-Box are stored in a ROM, it offers a shorter critical depth, it is suitable for FPGA implementation in terms of gate count. In high speed pipelined designs unbreakable delay of LUT becomes a drawback. The efficiency of AES hardware implementation in terms of speed, security, size, and power consumption largely depends on its architecture Every attempt has been made by researchers to optimize one or more parameters for some specific application, either to reduce the chip area, power consumption or to increase efficiency, throughput, and security level. The different applications of society requirements demand different parameters with respect to size for mobile applications, high-speed processing for a quick response. S-Box transformation in AES Implementation is the nonlinear transformation and it provides confusion part in encryption of data processing and contributes a significant part in achieving high security. CFA-based optimization is used for reducing the area for FPGA or VLSI designs for compact mobile applications, the data security is ensured by adopting different masking techniques.

Keywords

SubByte InvSubByte Multi-Variable Pattern Common Sub-expression Elimination (MVP-CSE) Composite field architecture (CFA) FPGA Masked S-Box Galois field (GF) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.University of Petroleum & Energy StudiesDehradunIndia
  2. 2.Guru Teg Bahadur Institute of TechnologyNew DelhiIndia
  3. 3.National Informatics CentreNew DelhiIndia

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