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Heterogeneous Integrations on Fan-Out RDL Substrates

  • John H. LauEmail author
Chapter

Abstract

As mentioned in Chap. 4 that TSV (through-silicon via) interposer is very expensive (Selvanayagam et al. in IEEE Trans Adv Pack 32(4), 2009, [1]; Chai et al. in IEEE Trans CPMT 1(5), 2011, [2]; Chien et al. in IMAPS Trans J Microelectron Pack 9, 2012, [3]; Chaware et al. in IEEE/ECTC Proc, 2012, [4]; Banijamali et al. in IEEE/ECTC Proc, 2011, [5]; Banijamali et al. in IEEE/ECTC Proc, 2012, [6]; Banijamali et al. in IEEE/ECTC Proc, 2013, [7]; Lau in 3D IC integration and packaging. McGraw-Hill, New York, 2016 [8]; Lau in Through-silicon via (TSV) for 3D integration. McGraw-Hill, New York, 2013, [9]; Lau in Reliability of RoHS compliant 2D & 3D IC interconnects. McGraw-Hill, New York, 2011, [10]) and a few silicon bridges have been proposed to replace the TSV interposers for heterogeneous integration applications. Recently, using the fan-out wafer/panel packaging technology (Lau in Fan-out wafer-level packaging. Springer, New York, 2018, [11]; Ko et al. in IEEE Trans CPMT, pp. 1561–1572, 2018, [12]; Lau et al. in IEEE Trans CPMT, pp. 1544–1560, 2018, [13]; Lau et al. in IMAPS Trans J Microelectron Electron Packag 15(4):148–162, 2018, [14]; Ko et al. in IEEE IMAPS Trans J Microelectron Electron Packag 15(4):141–147, 2018, [15]; Yoon et al. in IEEE/ECTC Proc: 1250–1254, 2012, [16]; Lau et al. in IEEE Trans CPMT 4(9):1407–1419, 2014, [17]; Lau et al. in IMAPS Trans J Microelectron Electron Packag:123–131, 2017, [18]; Lau et al. in IEEE Trans CPMT:991–1002, 2018, [19]; Lin et al. in IEEE/ECTC Proc:13–18, 2016, [20]) to make RDLs (redistribution-layers) on substrates to eliminate the TSV-interposer for heterogeneous integrations has been getting traction. At ECTC2013, Statschippac proposed using the fan-out flip chip to make the RDLs for the chips to perform mostly lateral communications. During ECTC2016, ASE and Mediatek used a similar technology to fabricate the RDLs with FOWLP and showed that the TSV interposer, wafer bumping, fluxing, chip-to-wafer bonding, cleaning, and underfill dispensing and curing are eliminated, i.e., TSV-less interposers. At ECTC2018, Samsung used chip-last or RDL-first to make the RDLs for the TSV-interposer. During SEMICON Taiwan 2018, TSMC also mentioned this technology and called it InFO_oS (integrated fan-out on substrate).

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.ASM Pacific TechnologyHong KongHong Kong

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