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Design and Implementation of ARQ Mechanism in High-Speed Data Acquisition System

  • Xiao LiEmail author
  • Jingyang Lv
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 550)

Abstract

The speed of high-speed railway in China is constantly increasing, and the demand for safety and reliability becomes more and more apparent. Therefore, it is especially important to collect and transmit high-speed data accurately, so high-speed data acquisition system emerged. Aiming at the problem of transmission packet loss in high-speed data acquisition system, a retransmission protocol is proposed for Automatic Repeat Request (ARQ) communication, which is implemented on field-programmable gate array (FPGA). This design compares several common retransmission protocols to select the optimal scheme. And the feasibility of the high-speed rail transponder system is analyzed. On the basis of that, this design takes full advantage of the flexibility and reconfigurability of the FPGA, uses the hardware description language VerilogHDL, uses Quartus II 13.1 for synthesis and routing, and finally verifies on the Cyclone VE series 5CEFA4F23F. The design has the advantages of convenient application and upgrade, good portability and versatility while solving the problem of packet loss.

Keywords

High-speed railways Gigabit Ethernet ARQ FPGA 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.School of Information and Communication EngineeringBeijing University of Posts and TelecommunicationsBeijingChina

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