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Multichannel High-Speed Data Caching System on FPGA for RAID Storage

  • Haixin Wang
  • Xue Bai
  • Qiongzhi WuEmail author
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 517)

Abstract

Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read–write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.

Keywords

Multichannel Caching system DDR3 FPGA 

References

  1. 1.
    JEDEC Solid State Technology Association: DDR3 SDRAM Specification (JESD79-3A). In: JEDEC Standard. September, 2007Google Scholar
  2. 2.
    Wang, B., Du, J., Bi, X., Tian, X.: High bandwidth memory interface design based on DDR3 SDRAM and FPGA. In: Soc Design Conference, pp. 253–254. IEEE (2016)Google Scholar
  3. 3.
    Xilinx. UG586: Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.2 User Guide. October 04, 2017Google Scholar
  4. 4.
    Jiao, S., Cheng, R.: Design of a DDR3 controller based on FPGA. Electron. Sci. Technol. 28(7), 41–43 (2015)Google Scholar
  5. 5.
    Ye, W., Li, H.: FPGA based DDR3 applications in a multichannel channelization data cache. In: International Symposium on Computational Intelligence and Design, pp. 54–57. IEEE (2017)Google Scholar
  6. 6.
    Xilinx. UG761: AXI Reference Guide v14.3. November 15, 2012Google Scholar
  7. 7.
    Ming, S., Zhao, Y., Lin, Q.: Design and optimization of DDR3 SDRAM controller based on FPGA. Electron. Sci. Technol. 29(11), 47–50 (2016)Google Scholar
  8. 8.
    Liu, S., Aseffa, D., Wu, C.: Performance considerations for writing data to solid-state drives. ICIC Express Lett. 10(3), 691–697 (2016)Google Scholar
  9. 9.
    Xilinx. WP469: Using the MicroBlaze Processor to Accelerate Cost-Sensitive Embedded System Development. June 06, 2016Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2020

Authors and Affiliations

  1. 1.School of Information and ElectronicsBeijing Institute of TechnologyBeijingChina

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