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RANK-Swapping Unblocked Row (RSR) Memory Controller

  • Arun S. TigadiEmail author
  • Hansraj Guhilot
  • Pramod Naik
Conference paper
Part of the Lecture Notes on Data Engineering and Communications Technologies book series (LNDECT, volume 28)

Abstract

The main parts of the current-day memory system are a memory controller and a memory device. The task of the controller is to coordinate the requests from the CPU, DMA, and other devices. Command bus and data bus act as a bridge between two components. The front end of the memory controller does the work of generating commands related to the respective request. The timing issue and arbitration of these commands are taken care by the back end of the memory controller. The critical requirement of these memory controllers is to provide service to all the requestors without violating timing issues. The real-time multi-core systems (Bui et al in Temporal isolation on multiprocessing architectures. IEEE, 2011) [1] have many resources shared between the cores. This makes timing analysis harder in case of these systems. We use different methods to analyze these systems and make the assumption that “Access latency of single request” doesn’t depend on different cores. The problem in deriving upper bounds is mainly due to the complex nature of multi-core systems [1]. These systems use DDR RAM as their main memory. These memories are partitioned into RANKS and BANKS which can support parallelism. Moreover, internal caching used by DRAM makes locality of references significant. The present memory controllers distribute memory request based on the command sequences generated, but in real time, this nature will not take advantage of locality. We will introduce a new design for a multi-core system for DDR devices. This employs RANK-swapping and open-row policies. The main advantage of this scheme is a significant reduction in the worst-case latency. This is mainly due to the creative RANK-switching mechanism. The memory is portioned into RANKS, BANKS, and rows to store an array of data. From this, we can isolate hard and soft requestors by assigning the same RANK to a respective type of requestors. This architectural improvisation improves the performance. Read–write latency can be taken out of the picture to improve bus utilization. By this technique, the latency for hard requestors is made predictable because it only depends upon a number of other requestors in the same RANK. Arbitration in hard requestor is mainly focused on latency in the worst case (Wu in Worst case analysis of DRAM latency in hard real-time systems, 2013) [2]. Arbitration for soft requestors is focused on throughput optimization.

Keywords

BANK RANK Real-time SDRAM FPGA 

Notes

Acknowledgements

I would like to thank Dr. Hansraj Guhilot for his motivation and valuable suggestions. I would also thank the principal, HOD E and C, and all the teaching and non-teaching staff of KLE Dr. M.S.S. CET, Belagavi, for their support in completing this work.

References

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.KLE Dr. M.S.S. CETBelagaviIndia
  2. 2.CoreEL Technologies PVT LTDBengaluruIndia

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