A Tunable Multiple Outputs FIR Filter Structure Realization

  • Pemmavit Sutthikarn
  • Sorawat ChivapreechaEmail author
  • Akraphon Trirat
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 547)


This paper proposes a design of a new finite impulse response (FIR) digital filter structure which gives 6-tunable frequency responses as 2 low-pass filters (LPF), 2 high-pass filters (HPF), 1 band-pass filter (BPF) and 1 band-stop filter (BSF) at the same time. The design procedure is initiated from 2 LPFs design. However in order to obtain a tunable filter, the unit delay is replaced by first-order single-multiplier structure for all-pass filter. Therefore, this new structure can be achieved and called tunable multiple outputs FIR filter. Finally, the amplitude responses that obtained from proposed structure can show the tunable capability using tuning parameter.


Tunable filter FIR filter Multiple outputs filter Digital filter All pass transformation 


  1. 1.
    Sorawat, C., Surapan, Y., Chusit, P., Kobchai, D.: FPGA implementation of multi-functional digital filter based on non-recursive scheme. In: Proceedings of the International Conference on Robotics, Vision, Information and Signal Processing: ROVISP 2005, Penang, Malaysia, 20–22 July 2005Google Scholar
  2. 2.
    Darak, S.J., Prasad, V.A., Lai, E.M.-K.: Efficient implementation of reconfigurable warped digital filters with variable low-pass, high-pass, bandpass, and bandstop responses. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(6), 1165–1169 (2013)CrossRefGoogle Scholar
  3. 3.
    Ambede, A., Vinod, A.P.: Design and implementation of high-speed all-pass transformation-based variable digital filters by breaking the dependence of operating frequency on filter order. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(5), 2008–2012 (2016)CrossRefGoogle Scholar
  4. 4.
    Ambede, A., Vinod, A.P.: Design of low complexity variable digital filters using first order all pass transformation and improved coefficient decimation method. In: 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), pp. 1–5, March 2014Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Pemmavit Sutthikarn
    • 1
  • Sorawat Chivapreecha
    • 1
    Email author
  • Akraphon Trirat
    • 1
  1. 1.Faculty of Engineering, Department of Telecommunication EngineeringKing Mongkut’s Institute of Technology LadkrabangBangkokThailand

Personalised recommendations