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Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power

  • Prateek GuptaEmail author
  • Shubham Kumar
  • Zia Abbas
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Abstract

In this paper, two one-bit full adder design techniques are explored for reduced power consumption in standby mode. The proposed algorithm based techniques compute optimal transistor sizing for variable operating conditions (temperature, supply voltage) to achieve desirable leakage power and speed for a full-adder circuit. Both techniques use ‘SLEEP’ signal to drive full adder circuit to lower standby mode leakage state without even degrading the performances in active mode. The investigation has been carried out for 45 nm, 32 nm, 22 nm Metal Gate High-K PTM models and all the simulation characterizations are carried out using HSPICE simulation tool. Performance comparison of both techniques after optimization has been done over a complete range temperature (−40 \(^\circ \)C−125 \(^\circ \)C) and ±5% variation in supply voltage. The resultant designs are tested on large full-adder based digital circuits to analyze the reduced standby leakage power. The results show that up to 97% of standby leakage reduction can be obtained with (0.4–15)% delay overhead using the proposed methods of full-adder design.

Keywords

CMOS Leakage power Propagation delay Minimum Leakage Vector (MLV) Input Vector Control (IVC) Power Gating (PG) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Center for VLSI and Embedded Systems Technologies (CVEST)International Institute of Information Technology, HyderabadHyderabadIndia

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