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A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications

  • M. Priyadharshni
  • S. KumaravelEmail author
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Abstract

Arithmetic units such as adders and multipliers play an essential role in the performance of Digital signal processor (DSP) systems. The efficiency of the Processors are influenced by the speed and power consumption of arithmetic units. It is improved by adopting approximate computing in arithmetic units with acceptable degradation in the output. Approximate computing is an emerging topic in the past decades, it aims to achieve promising design approach with the sacrifices in computational quality for error resilient applications. Approximate computing can be adopted both in hardware level and software level of research. This paper provides an elaborative investigation about approximate computing on full adders which is explored at the hardware level. The approximation is applied to full adders either at gate level or transistor level. Further, ripple carry adder is designed for varying bit width with different degrees of approximation using these approximate Full adders. Ripple carry adder is estimated based on the structural analysis such as Area, Delay Product (ADP) and Power, Delay Product (PDP) and error matrix such as pass rate, error rate, Normalized Error Distance (NED) and Mean Error Distance (MED). The ripple carry adders are designed in Verilog HDL and stimulated in Synopsys Design Compiler (DC) using tsmc 65 nm standard cell library typical corner whereas, the error characteristics is done in MATLAB.

Keywords

Approximate computing Approximate full adder Error matrix Ripple carry adder Structural analysis 

References

  1. 1.
    Almurib, H.A., Kumar, T.N., Lombardi, F.: Inexact designs for approximate low power addition by cell replacement. In: 2016 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 660–665. IEEE (2016)Google Scholar
  2. 2.
    Dutt, S., Nandi, S., Trivedi, G.: Analysis and design of adders for approximate computing. ACM Trans. Embed. Comput. Syst. (TECS) 17(2), 40 (2018)Google Scholar
  3. 3.
    Gupta, V., Mohapatra, D., Raghunathan, A., Roy, K.: Low-power digital signal processing using approximate adders. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 32(1), 124–137 (2013)CrossRefGoogle Scholar
  4. 4.
    Liang, J., Han, J., Lombardi, F.: New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Comput. 62(9), 1760–1771 (2013)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Mittal, S.: A survey of techniques for approximate computing. ACM Comput. Surv. (CSUR) 48(4), 62 (2016)Google Scholar
  6. 6.
    Oklobdzija, V.: The Computer Engineering Handbook. Computer Engineering Series. CRC Press, Boca Raton (2001)Google Scholar
  7. 7.
    Parhami, B.: Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press, Inc., New York (2009)Google Scholar
  8. 8.
    Townsend, W.J., Swartzlander, E.E., Abraham, J.A.: A comparison of Dadda and Wallace multiplier delays. In: Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, vol. 5205, pp. 552–561. International Society for Optics and Photonics (2003)Google Scholar
  9. 9.
    Verma, A.K., Brisk, P., Ienne, P.: Variable latency speculative addition: a new paradigm for arithmetic circuit design. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1250–1255. ACM (2008)Google Scholar
  10. 10.
    Yang, Z., Jain, A., Liang, J., Han, J., Lombardi, F.: Approximate XOR/XNOR-based adders for inexact computing. In: 2013 13th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 690–693. IEEE (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.VITVelloreIndia

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