A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) Testing
Promising nanoelectronic memories such as PCRAM, STT-RAM, Ferroelectric FET Memory and Resistive Random Access Memory (RRAM) are capable of substituting the conventional memory technologies such as SRAMs, DRAMs and flash memory in future computers. Among all these nanoelectronic memories RRAM results in higher density, lower power consumption, higher speed and better scalability which can fulfill the requirements of massive data growth as well as storage. But it is expected to go through numerous faults that reduce the reliability of the system. These faults may arise at any element of the memory system which includes the marginal circuits, inter junction and memory cell array. Read 1 Disturbance (R1D) fault is one among the main faults in RRAM that occurs, if the read value is 0 when 1 is the actual result which is kind of low resistance defect. In RRAM SET voltage (VSET), bit line voltage, restricted thermal stability and accumulated read current pulse leads to read disturbance faults and also when maximum current is applied for a read operation that immediately induces the read disturbance fault. As the read current and write current have the same path, read disturbance faults makes a bit flip. The accumulated effect of this read ‘1’ disturbance degrades the memory reliability. This kind of fault changes the value stored in a particular memory cell which leads to consequent inaccurate read values that keep on propagates till a new logic value is written in the same cell. Read disturbance lies between the read operation and read disturbance fault which is a major concern of today’s NVM since it directly affects the performance of the system. According to march C* test algorithm HfO2 based 1T1R RRAM’s R1D faults can be sensitized by ensuring the presence of ‘1’ (read 1) after the write ‘1’ operation and detected by another read 1 operation. In this article a novel March C2RR algorithm is proposed, here read operation is repeated twice in the second, fourth memory element (R3, R4 in M3 and R5, R6 in M4) and 100% fault coverage is achieved by the proposed method that detects R1D faults and all the random faults effectively.
KeywordsNanoelectronic memory RRAM R1D fault SET RESET operation Fault coverage Test complexity
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