A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design
This work presents a new bit-interleaving low-power 11T subthreshold SRAM cell with the Data-Dependent Partial-Feedback Cutting to improve the write ability. The isolated read path of 11T enhances the read static noise margin (RSNM) which is equivalent to that of its hold SNM (HSNM), while the incorporated PMOS stacking in each of the inverter helps to reduce the leakage power of the cell. The half-select free behavior of the proposed 11T cell facilitates the bit-interleaving architecture of memory array that reduces the multi-bits error occurrence in a single word of data, and thus enhance the soft error tolerance. Using the proposed cell, a four-input FPGA lookup table (LUT) has been implemented working on 0.4V supply, which consumes 0.59\(\times \) less leakage power as compared to that of 6T LUT. Finally, a two adjacent bits error correction technique is also suggested to incorporate with the proposed bit-interleaving 11T array, so that the effect of soft error can almost be neglected. It consumes comparable leakage and read access energy to that of one-bit error correcting conventional hamming code.
KeywordsStatic Random Access Memory (SRAM) Static noise margin (SNM) Leakage power Field Programmable Gate Array (FPGA) Soft error correction
The authors would like to thank Special Manpower Development Program for Chips to System Design (SMDP-C2SD) research project of Department of Electronics and Information Technology (DEITY) under Ministry of Communication and Information Technology, Government of India to provide the lab facilities.
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