Low Leakage Noise Tolerant 10T SRAM Cell
This paper presents a low leakage noise tolerant (LL10T) SRAM cell. The proposed SRAM cell has high read static noise margin and low leakage power in contrast to the conventional 6T (C6T) SRAM cell. LL10T isolates the read circuitry through read decoupling technique to improve the read static noise margin by reducing the disturbance in read operation. The proposed cell also prevents false discharging of read bitline while reading high logic using data dependent charge pump circuit. Further, a sleep transistor is used in read circuitry that remains off in hold and write operation to reduce the leakage power consumption in proposed SRAM cell. A separated write circuitry is suggested to enhance the write operation. Simulation results show that LL10T SRAM cell offers 2.1x higher read static noise margin and 5.9x less leakage power over C6T SRAM cell. The proposed SRAM cell is also compared with low power (LP8T) SRAM cell. LL10T SRAM cell offers 33.6x higher hold static noise margin and 4.7x less leakage power. However it has 4x and 2.9x longer delay over C6T and LP8T SRAM cells respectively due to single read bitline and increased node capacitance in read path. Simulations were performed using HSPICE at 32-nm PTM technology at supply voltage of 900 mV. So, this SRAM cell may be suitable for applications which demand low power noise tolerant, enhanced stability and moderate speed SRAM cell at sub-micrometer technology.
KeywordsCharge pump circuit Stacking effect Static leakage Write ability Sleep transistor
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