Efficient and Failure Aware ECC for STT-MRAM Cache Memory
Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a favorable memory technology for on-chip cache hierarchies in multi-core processors. STT-MRAM offers scalability, near zero leakage power, non-volatility, high density, etc. which makes it a good candidate for on-chip cache memory. However, write operation in STT-MRAM is asymmetric which causes multiple errors in single line of cache (up to 70 bits of errors). For this usually error control codes are used. In this paper, we focus on analyzing the effectiveness of BCH codes in rectifying the write errors of STT-MRAM. So in the current work (1216, 512) BCH encoder and decoder are designed and verified at the RTL level using Verilog HDL. For encoder, the conventional linear feedback shift register (LFSR) structure is used and for decoding Meggitt decoder is used which also requires 2 LFSR one for first-time syndrome calculation and another for spontaneous recalculation of the syndrome. In our proposed technique, we have reused the syndrome calculator as spontaneous calculator thereby reducing the area. It is practically impossible to manually write Verilog code for designing large architectures such as the (1216, 512) BCH decoder. We have solved this problem by writing a Matlab script which takes the code and data sizes as input, gives the Verilog code as output. We have synthesized the BCH encoder and decoder at 32 nm technology using synopsis design compiler and estimated area, power and delay of the encoder and decoder.
KeywordsSTT-MRAM Error control coding (ECC) BCH encoder and decoder Meggitt decoder
This work is partly supported by SMDPC2SD project, sponsored by Ministry of Electronics & Information of Technology, Government of India.
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