Advertisement

Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices

  • Rahul ShresthaEmail author
  • Ashutosh Sharma
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Abstract

This work presents new flexible-architecture for maximum-a-posteriori (MAP) decoder with multi-radix modes to support various throughputs at different levels of power consumption. We have designed major internal blocks of MAP decoder using extensive steering logic to support radix-2/4/8 operating modes. These designs enable efficient clock-gating of our decoder for low-power consumption in different operating modes. This decoder-architecture is post-layout simulated in 65 nm-CMOS process and its performance analysis showed that the bit-error-rate (BER) of 10\(^{-4}\) could be achieved at 5 dB. Implementation result shows that the suggested MAP decoder could achieve throughput in the range 270−810 Mbps with the corresponding power consumption range of 12.24−37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption.

Keywords

Wireless communication Channel codes MAP decoding VLSI architectures VLSI design 

Notes

Acknowledgement

The authors would like to thank Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Govt. of India, for supporting this research work.

References

  1. 1.
    Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon limit error correcting coding and decoding: turbo codes. In: Proceedings of IEEE International Conference on Communications, vol. 40, no. 8, pp. 1064–1070 (1993)Google Scholar
  2. 2.
    Shrestha, R., Paily, R.P.: High-throughput turbo decoder with parallel architecture for LTE wireless communication standards. IEEE Trans. Circ. Syst. I Reg. Papers 61(9), 2699–2710 (2014)CrossRefGoogle Scholar
  3. 3.
    Ilnseher, T., Kienle, F., Weis, C., Wehn, N.: A 2.15 GBit/s turbo code decoder for LTE advanced base station applications. In: Proceedings of International Symposium on Turbo Codes and Iterative Information Processing (ISTC), pp. 21–25 (2012)Google Scholar
  4. 4.
    Boccardi, F., Heath, R.W., Lozano, A., Marzetta, T.L., Popovski, P.: Five disruptive technology directions for 5G. IEEE Commun. Mag. 52(2), 74–80 (2014)CrossRefGoogle Scholar
  5. 5.
    Bahl, L.R., Cocke, J., Jelinek, F., Raviv, J.: Optimal decoding of linear codes for minimizing symbol error rate. IEEE Trans. Inf. Theory 20(2), 284–287 (1974)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Lin, C.-H., Chen, C.-Y., Wu, A.-Y.: Area-efficient scalable MAP processor design for high-throughput multistandard convolutional turbo decoding. IEEE Trans. Very Large Scale Integr. (VLSI) 19(2), 305–318 (2017)Google Scholar
  7. 7.
    3GPP; Technical Specification Group Radio Access Network, “E-UTRA; Multiplexing and Channel Coding (Release 10) 3GPP,” 3GPP, TS 36.212, Rev. 10.0.0 (2011) StdGoogle Scholar
  8. 8.
    Bhat, P., et al.: LTE-advanced: an operator perspective. IEEE Commun. Mag. 50(2), 104–114 (2012)CrossRefGoogle Scholar
  9. 9.
    Woodard, J.P., Hanzo, L.: Comparative study of turbo decoding techniques: an overview. IEEE Trans. Veh. Technol. 49(6), 2208–2233 (2000)CrossRefGoogle Scholar
  10. 10.
    Benkeser, C., Burg, A., Cupaiuolo, T., Huang, Q.: Design and optimization of an HSDPA turbo decoder ASIC. IEEE J. Solid-State Circ. 44(1), 98–106 (2009)CrossRefGoogle Scholar
  11. 11.
    Studer, C., Benkeser, C., Belfanti, S., Huang, Q.: Design and implementation of a parallel turbo-decoder ASIC for 3GPP-LTE. IEEE J. Solid-State Circ. 46(1), 8–17 (2011)CrossRefGoogle Scholar
  12. 12.
    Sun, Y., Zhu, Y., Goel, M., Cavallaro, J.R.: Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. In: Proceedings of International Conference on Application-Specific Systems, Architectures and Processors, pp. 209–214 (2008)Google Scholar
  13. 13.
    Lee, S.-J., Shanbhag, N.R., Singer, A.C.: A 285-MHz pipelined MAP decoder in 0.18 um CMOS. IEEE J. Solid-State Circ. 40(8), 1718–1725 (2005)CrossRefGoogle Scholar
  14. 14.
    Tang, C.-H., Wong, C.-C., Chen, C.-L., Lin, C.-C., Chang, H.-C.: A 952MS/s max-log MAP decoder chip using radix-4.4 ACS architecture. In: Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 79–82 (2006)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.School of Computing and Electrical EngineeringIndian Institute of Technology (IIT) MandiMandiIndia
  2. 2.Center for VLSI and Embedded System TechnologiesInternational Institute of Information Technology (IIIT) HyderabadHyderabadIndia

Personalised recommendations