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LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits

  • Zia AbbasEmail author
  • Andleeb Zahra
  • Mauro Olivieri
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Abstract

Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 103 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.

Keywords

NBTI PBTI Leakage current VHDL CMOS 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Center for VLSI and Embedded System Technologies (CVEST)IIIT HyderabadHyderabadIndia
  2. 2.DIETSapienza University of RomeRomeItaly

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