Advertisement

Robust SRAM Cell Development for Single-Event Multiple Effects

  • Naga Raghuram CHEmail author
  • D. Manohar Reddy
  • Puli Kishore Kumar
  • Gaurav Kaushal
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Abstract

As the transistor size scales down exponentially to Nanometric dimensions, the susceptibility of electronic circuits to radiation increases drastically. Static-Random-Access Memories (SRAMs) are applicable in the areas of aerospace and space applications where their performance must meet the increased data rates and must be resilient to radiation exposures to guarantee reliability. Therefore, development of resilient SRAM is a challenging and demanding problem. In this paper a robust 10T SRAM (RHD10T) is proposed and compared with the existing radiation hardened (rad-hard) SRAM circuits. The proposed RHD10T SRAM is more robust towards Single Event Multiple Effects (SEME’s) compared with the recently published literature. Further, it takes 29% lesser area with respect to the standard DICE cell. In contrast to latest rad-hard SRAM cells, the proposed RHD10T cell is delivering 99.8% less failure probability for the applied charge distribution. Process variations (PV) show least effects when compared to 6T SRAM cell.

Index Terms

Single event upset Radiation hardening Single-Event Multiple Effect (SEME) Robust SRAM cell 

References

  1. 1.
    Berkeley predictive technology model. http://www.eas.asu.edu/ptm/
  2. 2.
    Alouani, I., Elsharkasy, W.M., Eltawil, A.M., Kurdahi, F.J., Niar, S.: AS8-static random ac-cess memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement. IET Circuits Dev. Syst. 11(1), 89–94 (2017)CrossRefGoogle Scholar
  3. 3.
    Amusan, O.A., Massengill, L.W., Baze, M.P., Bhuva, B.L., Witulski, A.F., Black, J.D., Bal-asubramanian, A., Casey, M.C., Black, D.A., Ahlbin, J.R., et al.: Mitigation techniques for single-event-induced charge sharing in a 90-nm bulk CMOS process. IEEE Trans. Dev. Mater. Reliab. 9(2), 311–317 (2009)CrossRefGoogle Scholar
  4. 4.
    Calin, T., Nicolaidis, M., Velazco, R.: Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nucl. Sci. 43(6), 2874–2878 (1996)CrossRefGoogle Scholar
  5. 5.
    Chengye, Z., Zhuangsi, W.: A novel reliable SEU hardened latch to mitigate multi-node charge collection. In: IET International Conference on Information Science and Control Engineering 2012 (ICISCE 2012), pp. 1–4, December 2012Google Scholar
  6. 6.
    Detcheverry, C., Dachs, C., Lorfevre, E., Sudre, C., Bruguier, G., Palau, J., Gasiot, J., Ecoffet, R.: SEU critical charge and sensitive area in a submicron CMOS technology. IEEE Trans. Nucl. Sci. 44(6), 2266–2273 (1997)CrossRefGoogle Scholar
  7. 7.
    Dodd, P.E., Massengill, L.W.: Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans. Nucl. Sci. 50(3), 583–602 (2003)CrossRefGoogle Scholar
  8. 8.
    Duzellier, S., Ecoffet, R.: Recent trends in single-event effect ground testing. IEEE Trans. Nucl. Sci. 43(2), 671–677 (1996)CrossRefGoogle Scholar
  9. 9.
    Fazeli, M., Ahmadian, S.N., Miremadi, S.G., Asadi, H., Tahoori, M.B.: Soft error rate estimation of digital circuits in the presence of multiple event transients (METs). In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–6. IEEE (2011)Google Scholar
  10. 10.
    Heijmen, T., Giot, D., Roche, P.: Factors that impact the critical charge of memory elements. In: 12th IEEE International On-Line Testing Symposium, IOLTS 2006, p. 6. IEEE (2006)Google Scholar
  11. 11.
    Katsarou, K., Tsiatouhas, Y.: Soft error interception latch: double node charge sharing SEU tolerant design. Electron. Lett. 51(4), 330–332 (2015)CrossRefGoogle Scholar
  12. 12.
    Kelin, L.H.H., Klas, L., Mounaim, B., Prasanthi, R., Linscott, I.R., Inan, U.S., Subhasish, M.: Leap: layout design through error-aware transistor positioning for soft-error resilient sequential cell design. In: 2010 IEEE International Reliability Physics Symposium (IRPS), pp. 203–212. IEEE (2010)Google Scholar
  13. 13.
    Lin, S., Kim, Y.B., Lombardi, F.: A 11-transistor nanoscale CMOS memory cell for hardening to soft errors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(5), 900–904 (2011)CrossRefGoogle Scholar
  14. 14.
    Lin, S., Kim, Y.B., Lombardi, F.: Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset. IEEE Trans. Dev. Mater. Reliab. 12(1), 68–77 (2012)CrossRefGoogle Scholar
  15. 15.
    Rajaei, R., Asgari, B., Tabandeh, M., Fazeli, M.: Design of robust SRAM cells against single-event multiple effects for nanometer technologies. IEEE Trans. Dev. Mater. Reliab. 15(3), 429–436 (2015)CrossRefGoogle Scholar
  16. 16.
    Rajaei, R., Tabandeh, M., Fazeli, M.: Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation. Microelectron. Reliab. 53(6), 912–924 (2013)CrossRefGoogle Scholar
  17. 17.
    Rajaei, R., Tabandeh, M., Fazeli, M.: Soft error rate estimation for combinational logic in presence of single event multiple transients. J. Circuits Syst. Comput. 23(06), 1450091 (2014)CrossRefGoogle Scholar
  18. 18.
    Rajaei, R., Tabandeh, M., Fazeli, M.: Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations. J. Circuits Syst. Comput. 24(01), 1550007 (2015)CrossRefGoogle Scholar
  19. 19.
    Reviriego, P., Maestro, J.A., Flanagan, M.F.: Error detection in majority logic decoding of euclidean geometry low density parity check (EG-LDPC) codes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(1), 156–159 (2013)CrossRefGoogle Scholar
  20. 20.
    Seifert, N., Ambrose, V., Gill, B., Shi, Q., Allmon, R., Recchia, C., Mukherjee, S., Nassif, N., Krause, J., Pickholtz, J., et al.: On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies. In: 2010 IEEE International Reliability Physics Symposium (IRPS), pp. 188–197. IEEE (2010)Google Scholar
  21. 21.
    Wang, W.: RC hardened FPGA configuration SRAM cell design. Electron. Lett. 40(9), 525–526 (2004)CrossRefGoogle Scholar
  22. 22.
    Yang, F.L., Saleh, R.A.: Simulation and analysis of transient faults in digital circuits. IEEE J. Solid-State Circuits 27(3), 258–264 (1992)CrossRefGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Naga Raghuram CH
    • 1
    Email author
  • D. Manohar Reddy
    • 1
  • Puli Kishore Kumar
    • 1
  • Gaurav Kaushal
    • 2
  1. 1.Department of Electronics and Communication EngineeringNational Institute of TechnologyPatnaIndia
  2. 2.Department of Electronics and Communication EngineeringABV-IIITMGwaliorIndia

Personalised recommendations