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Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks

  • R. Sree RanjaniEmail author
  • M. Nirmala Devi
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Abstract

The vulnerability of hardware Trojans in digital integrated circuits (IC) and their prevention methods are studied in the past decade. The focus of this work is to prevent the hardware Trojan insertion by a built-in locking mechanism known as hardware encryption. The main objective of the techniques proposed is to build a secured logical locking such that (i) an incorrect key will result a functionally locked design and (ii) it is difficult to attain the secret key. In order to build a strong hardware encryption technique, the locking key is to be placed at high observable nodes of the design. Furthermore, the proposed scheme will address the key-guessing attacks like Brute force attack, Hill climbing attack and as well as path sensitization attacks, and provide the corresponding countermeasures. Experimental results present a highly secured locking mechanism with acceptable design overhead, when the proposed technique is employed on ISCAS’85 benchmark circuits.

Keywords

Hardware locking Key-gates insertion High observability nodes Output corruption Design-for-security 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringAmrita School of EngineeringCoimbatoreIndia
  2. 2.Amrita Vishwa VidyapeethamCoimbatoreIndia

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