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A 12.5-Gb/s Equalizer with CTLE and a 4-Tap Quarter-Rate DFE in 40 nm Technology

  • Qing Xu
  • Jianjun ChenEmail author
  • Yueyue Chen
  • Bin Liang
  • Bo Xiong
  • Yuan Luo
  • Jizuo Zhang
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 994)

Abstract

On account of finite channel bandwidth and reflection, receiver cannot receive data accurately resulting from ISI. To satisfy the transmission requirements of PCIE3.1 and Rapid IO3.2, this paper presents a 12.5 Gb/s equalizer based on 40 nm CMOS. It uses Continuous-Time Linear Equalizer (CTLE) and a quarter-baud-rate decision feedback equalizer (DFE) with 4 taps. Finally, the receiver can effectively balance data and restore eye diagram with a channel loss of 28 dB at 12.5 Gb/s. The layout area of equalizer is 0.66 mm2, and its consumption is 33.08 mW from a 1.1-V supply.

Keywords

Equalizers DFE CTLE ISI Data eye 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Qing Xu
    • 1
  • Jianjun Chen
    • 1
    Email author
  • Yueyue Chen
    • 1
  • Bin Liang
    • 1
  • Bo Xiong
    • 1
  • Yuan Luo
    • 1
  • Jizuo Zhang
    • 1
  1. 1.School of ComputerNational University of Defense TechnologyChangshaPeople’s Republic of China

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