Energy-Efficient SRAM Cell Design with Body Biasing

  • P. KalyaniEmail author
  • M. Madhavi Latha
  • P. Chandra Sekhar
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 65)


This paper presents the need of high-speed SRAM memory operation for minimum supply voltage. The reduction of power dissipation in memories is becoming primary importance in subthreshold region. There are several power reduction techniques which can be applied to SRAM memory cell to design low-power and energy-efficient memory. SRAM cell is designed with body biasing technique and used in the memory array to improve performance. The 32 × 32 SRAM memory array is implemented using cadence 45 nm technology. Simulation and analysis results are compared with conventional array for better performance.


SRAM Subthreshold memory Body biasing PVT Static noise margin Leakage current Peripherals 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • P. Kalyani
    • 1
    Email author
  • M. Madhavi Latha
    • 1
  • P. Chandra Sekhar
    • 2
  1. 1.Electronics and Communication EngineeringJNTUHHyderabadIndia
  2. 2.Electronics and Communication EngineeringOsmania UniversityHyderabadIndia

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