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FPGA Implementation of Speculative Prefix Accumulation-Driven RNS for High-Performance FIR Filter

  • G. Reddy HemanthaEmail author
  • S. Varadarajan
  • M. N. Giri Prasad
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 65)

Abstract

In this paper, we present speculation-driven prefix topology-based finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The core objective of our proposed framework is to maximize the prefix accumulation in the application of RNS to the design high-performance FIR filter design. To achieve this, we propose a RAM-based reverse conversion model followed by accumulation to produce the modular multiplication. The proposed RNS design makes use of block RAMs available in FPGA devices and appropriate moduli sets in order to accommodate FIR convolution results. The proposed approach is formulated to design precomputed reverse converters for different moduli sets and to implement FPGA as target devices. As a result, we propose speculative parallel prefix topology-based post accumulation technique for RNS-based multiplication, along with a high-performance FIR filter architecture that employs independent modulo channel RNS arithmetic. Experiment results of RNS-FIR design over different number of FIR taps and input operand word lengths alongside with appropriate moduli sets that suits to accommodate FIR end results.

Keywords

Parallel prefix adder FIR filter RNS system Speculation 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • G. Reddy Hemantha
    • 1
    Email author
  • S. Varadarajan
    • 2
  • M. N. Giri Prasad
    • 3
  1. 1.Department of ECEJawaharlal Nehru Technological University AnanthapurAnanthapuramuIndia
  2. 2.Department of ECE, SVU College of EngineeringS V UniversityTirupatiIndia
  3. 3.Department of ECE, JNTU College of EngineeringJawaharlal Nehru Technological University AnanthapurAnanthapuramuIndia

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