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Low-Power and High-Speed Configurable Arithmetic and Logic Unit

  • Naveen Kumar KabraEmail author
  • Zuber M. Patel
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 65)

Abstract

Low power and high speed are critical design issues in the field of microprocessor design. Arithmetic and logic unit (ALU) is one of the most power and delay consuming elements of microprocessor. Conventional approach to design an ALU of microprocessor uses two different units to perform arithmetic and logical operation, respectively. Arithmetic unit is designed with adders while logical unit with logic gates. Adders are selected as per the application requirement based on VLSI matrices. In this paper, we present configurable ALU that improves performance in terms of speed and power. To achieve the objective, configurable ALU uses two adders to perform the same task. We also present a method to increase the number of logical operations. In the proposed design, eight arithmetic and eight logical operations are performed with 4-bit binary data. The proposed design is verified using Xilinx ISE 14.7 design suite and synthesized by genus synthesis solution of cadence at GDPK-45 nm technology. The proposed work offers saving up to 21.196%, up to 20.312%, and up to 6.288% in power, area, and delay, respectively.

Keywords

Configurable ALU Low power High speed CLA RCA Multiplexer 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Sardar Vallabhbhai National Institute of Technology SuratSuratIndia

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