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A Novel Architecture of High-Speed and Area-Efficient Wallace Tree Multiplier Using Square Root Carry Select Adder with Mirror Adder

  • Yamini Devi YkuntamEmail author
  • M. Rajan Babu
Conference paper
Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 65)

Abstract

Multipliers are important blocks in designing various digital and high-performance systems, such as processors, signal processing circuits, communication systems. To design high-performance systems, the multiplier used in them should be designed efficiently. Among various multiplier designs, Wallace tree multiplier is fastest in operation. The adder is the main circuit in any multiplier design whose speed of operation affects the performance of multiplier. Among different adder topologies, Square root Carry Select Adder (SQRT CSLA) is good in performance which can be used in the Wallace tree multiplier design as adder block to achieve high performance. In this proposed multiplier design, SQRT CSLA block is modified by replacing Ripple Carry Adder blocks with mirror adder and Binary to Excess-1 Converter (BEC) in order to achieve high performance and less area. Wallace tree multipliers of 4-bit and 8-bit are designed in Verilog. The proposed multiplier is functionally verified using Xilinx ISIM simulator and later synthesized using XST synthesizer in Xilinx ISE design suite. The proposed design of multiplier is compared with at present Wallace tree multiplier designs in terms of number of LUTs and delay (ns).

Keywords

Wallace tree multiplier Ripple carry adder Square root carry select adder Binary to excess one converter Mirror adder 

References

  1. 1.
    Weste N, Harris D (2004) CMOS VLSI design. Addison Wesley, ReadingGoogle Scholar
  2. 2.
    Weste N, Eshragian K (1985–1993) Principles of CMOS VLSI designs: a system perspective, 2nd edn. Addison-WesleyGoogle Scholar
  3. 3.
    Ercegovac MD, Lang T (2004) Digital arthimetic. Morgan Kaufmann, Elsevier Inc.Google Scholar
  4. 4.
    Bansal H, Sharma KG, Sharma T (2014) Wallace tree multiplier designs: a performance comparison review. Innov Syst Des Eng 5(5)Google Scholar
  5. 5.
    Uma R, Vijayan V, Mohanapriya M, Paul S (2012) Area, delay and power comparison of adder topologies. Int J VLSI Des Commun Syst (VLSICS) 3(1)Google Scholar
  6. 6.
    Rabaey JM (2001) Digtal integrated circuits—a design perspective. Prentice-Hall, Upper Saddle RiverGoogle Scholar
  7. 7.
    Ykuntam YD (2016) High speed & area efficient square root carry select adder with mirror adder. NCRCECTGoogle Scholar
  8. 8.
    He Y, Chang CH, Gu J (2005) An area efficient 64-bit square root carry-select adder for low power applications. In: Proceedings of international symposium on circuits and systems, vol 4, pp 4082–4085Google Scholar
  9. 9.
    Ramkumar B, Kittur HM (2012) Low-power and area-efficient carry select adder. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(2)CrossRefGoogle Scholar
  10. 10.
    Ykuntam YD, Nageswara Rao M, Locharla GR (2013) Design of 32-bit carry select adder with reduced area. IJCA 75(2)Google Scholar
  11. 11.
    Bala Sai Kesava R, Lingeswara Rao B, Bala Sindhuri K, Udaya Kumar N (2016) Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter. In: 2016 IEEE conference on advances in signal processing (CASP), Cummins College of Engineering for WomenGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of ECELendi Institute of Engineering and TechnologyVizianagaramIndia

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