Design of FIR Filter Architecture for Fixed and Reconfigurable Applications Using Highly Efficient Carry Select Adder

  • Shaurav ShahEmail author
  • Swaminadhan Rajula
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 898)


With increased complexity in digital circuits, efficient performance of involved circuitry has become the part and parcel of the digital signal processors (DSPs). In this paper, we have designed an efficient FIR filter for fixed and reconfigurable applications by embedding an area, and delay efficient carry select adder (CSLA), implemented by optimizing the redundancies in the logical operations in conventional and BEC-based CSLA. The proposed CSLA involves less area and delay than BEC-based CSLA and conventional CSLA. Here the carry operation is scheduled before the ultimate sum unlike the traditional method. Having desirably less output area and delay this becomes the best choice for FIR filter of transpose form. For the reconfigurable filter design, it is seen that the delay is reduced by 26.66%, and for MCM-based filter, the delay is reduced by 20.23%. The efficacy of the proposed design is accompanied by 15% reduction in area.


Finite impulse response (FIR) filters Carry select adder (CSLA) Half summation generator (HSG) Half carry generator (HCG) Add carry generator (ACG) Common sub-expression elimination (CSE) 


  1. 1.
    Vinod, A.P., Lai, E.M.: Low power and high-speed implementation of FIR filters for software defined radio receivers. IEEE Trans. Wirel. Commun. 7(5), 1669–1675 (2006)CrossRefGoogle Scholar
  2. 2.
    Sivaranjini, K., Jacob, N.S., Unnikrishnan, G., Heera, K.H.: Low power, high speed FIR filter design. Int. J. Appl. Eng. Res. 10, 440–444 (2015)Google Scholar
  3. 3.
    Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, New York, NY, USA (1999)Google Scholar
  4. 4.
    Manju, S., Sornagopal, V.: An efficient SQRT architecture of carry select adder design by common Boolean logic. In: Proceedings of VLSI ICEVENT, 2013, pp. 1–5 (2013)Google Scholar
  5. 5.
    Ramkumar, B., Kittur, H.M.: Low-power and area-efficient carry-select adder. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(2), 371–375 (2012)CrossRefGoogle Scholar
  6. 6.
    Kim, Y., Kim, L.-S.: 64-bit carry-select adder with reduced area. Electron. Lett. 37(10), 614–615 (2001)CrossRefGoogle Scholar
  7. 7.
    He, Y., Chang, C.H., Gu, J.: An area-efficient 64-bit square root carry-select adder for low power application. In: Proceedings of IEEE International Symposium on Circuits Systems, 2005, vol. 4, pp. 4082–4085Google Scholar
  8. 8.
    Mohanty, B.K., Meher, P.K.: A high-performance FIR filter architecture for fixed and reconfigurable applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(2) (2016)CrossRefGoogle Scholar
  9. 9.
    Karthick, S., Valarmathy, S., Prabhu E.: Reconfigurable FIR filter with radix-4 array multiplier. J. Theor. Appl. Inf. Technol. 57, 326–336 (2013)Google Scholar
  10. 10.
    Mahesh, R., Vinod, A.P.: A new common subexpression elimination. Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), 217–219 (2008)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics & Communication EngineeringAmrita School of Engineering, Amrita Vishwa VidyapeethamBengaluruIndia

Personalised recommendations