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Design of FIR Filter Architecture for Fixed and Reconfigurable Applications Using Highly Efficient Carry Select Adder

  • Shaurav ShahEmail author
  • Swaminadhan Rajula
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 898)

Abstract

With increased complexity in digital circuits, efficient performance of involved circuitry has become the part and parcel of the digital signal processors (DSPs). In this paper, we have designed an efficient FIR filter for fixed and reconfigurable applications by embedding an area, and delay efficient carry select adder (CSLA), implemented by optimizing the redundancies in the logical operations in conventional and BEC-based CSLA. The proposed CSLA involves less area and delay than BEC-based CSLA and conventional CSLA. Here the carry operation is scheduled before the ultimate sum unlike the traditional method. Having desirably less output area and delay this becomes the best choice for FIR filter of transpose form. For the reconfigurable filter design, it is seen that the delay is reduced by 26.66%, and for MCM-based filter, the delay is reduced by 20.23%. The efficacy of the proposed design is accompanied by 15% reduction in area.

Keywords

Finite impulse response (FIR) filters Carry select adder (CSLA) Half summation generator (HSG) Half carry generator (HCG) Add carry generator (ACG) Common sub-expression elimination (CSE) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics & Communication EngineeringAmrita School of Engineering, Amrita Vishwa VidyapeethamBengaluruIndia

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