Advertisement

Security Systems in Design for Testing

  • M. I. ShinyEmail author
  • R. Reshma
  • Shine Ross
  • Siji John
  • R. Sreevidya
  • Sumana Moothedeth
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 898)

Abstract

It has become a great problem nowadays that the information contained in an IC chip is not provided with adequate security against the cunning attackers. The modern chip designs inbuilt with a design for testing (DfT) that enable testing process to become more easier, but it also acts as backdoor tool to the hackers to retrieve the sensitive data from the chip. So, in order for providing security for the information contained in the chip, we introduce a reconfigurable PUF design technique with the DfT. This security is achieved by providing a barrier against the hamming distance-based attack. In this paper, we compare the analysis of modified linear feedback shift registers (LFSRs), pseudorandom sequence generator, and physical unclonable function (PUF) in terms of randomness, hamming distance, and security. The result of comparison provides the PUF design have maximum security without effecting the testability of the circuits.

Keywords

Linear feedback shift register Physical unclonable function Design for testing 

References

  1. 1.
    Hely, D., Flottes, M.-L., Frederic, B., Rouzeyre, B., Berard, N., Renovell, M.: Scan design and secure chip. In: IOLTS, vol. 4, pp. 219–224 (2004)Google Scholar
  2. 2.
    John, P.K.: BIST architecture for multiple RAMs in SoC. Proc. Comput. Sci. 115, 159–165 (2017)CrossRefGoogle Scholar
  3. 3.
    Haridas, N., Nirmala Devi, M.: Efficient linear feedback shift register design for pseudo exhaustive test generation. In: BIST 3rd IEEE International Conference Electronics Computer Technology (ICECT), vol. 1 (2011)Google Scholar
  4. 4.
    Shaer, L., et al.: A low power reconfigurable LFSR. In: 18th Mediterranean IEEE Electrotechnical Conference (MELECON) (2016)Google Scholar
  5. 5.
    Shiny, M.I., Nirmala, D.M.: LFSR based secured scan design testability techniques. Proc. Comput. Sci. 115, 174–181 (2017)CrossRefGoogle Scholar
  6. 6.
    Suh, G.E., Clarke, D., Gassend, B., van Dijk, M., Devadas, S.: Efficient memory integrity verification and encryption for secure processors. In: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p. 339. IEEE Computer Society (2003)Google Scholar
  7. 7.
    Guajardo, J., Kumar, S.S., Schrijen, G.-J., Tuyls, P.: Physical unclonable functions and public-key crypto for FPGA IP protection. In: FPL 2007 International Conference on Field Programmable Logic and Applications, 2007, pp. 189–195. IEEE (2007)Google Scholar
  8. 8.
    Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th annual Design Automation Conference, DAC ’07 (2007)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • M. I. Shiny
    • 1
    Email author
  • R. Reshma
    • 1
  • Shine Ross
    • 1
  • Siji John
    • 1
  • R. Sreevidya
    • 1
  • Sumana Moothedeth
    • 1
  1. 1.Department of Electronics and Communication EngineeringJyothi Engineering CollegeCheruthuruthy, ThrissurIndia

Personalised recommendations