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FPGA Implementation of Coding for Minimizing Delay and Power in SOC Interconnects

  • N. ChintaiahEmail author
  • G. Umamaheswara Reddy
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 898)

Abstract

In this paper, the bus encoding technique is introduced to reduce the number of transitions. The data word transmission on an on-chip bus causes the switching of data bits on the bus wires. This switching charges and discharges the capacitance associated with the wires and consequently causes dynamic power dissipation and increase in delay. A substantial amount of power is dissipated from buses compared with the power dissipation of the remaining circuit. The data bits sent through these buses should be encoded to decrease the switching activity, thereby reducing the power consumption and delay of the buses. In this approach, encoding is widely used to reduce the number of transitions. The encoder comprises four subdivisions, and the average power conserved was 10.17%. Overall, the average delay is decreased by 4.5%. Therefore, more amount of average power is conserved, and the delay is shortened.

Keywords

Crosstalk Encoder Path delay Even–odd inversion Upper–lower inversion 

References

  1. 1.
    Stan, M.R., Burleson, W.P.: Bus invert coding for low power I/O. IEEE Trans. Very Large Scale Int. Syst. 3, 49–58 (1995)CrossRefGoogle Scholar
  2. 2.
    Kim, K.W., Beck, K.H., Shanbhag, N., Liu, C.L., Kang, S.M.: Coupling-driven signal encoding scheme for low power interface design. In: IEEE/ACM International Conference on Computer-aided Design. 318–321 (2000)Google Scholar
  3. 3.
    Ramprasad, S., Shanbhag, N.R., Hajj, I.N.: A coding framework for low-power address and data busses. IEEE Trans. Very Large Scale Integr. Syst. 7, 212–221 (1999)CrossRefGoogle Scholar
  4. 4.
    Benini, L., Micheli, G.De., Macii, E., Sciuto, D., Silvano, C.: Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems. In: Proceedings of IEEE/ACM Great Lakes Symposium on VLSI (GLS-VLSI), Urbana, IL. pp. 77–82, Mar 1997Google Scholar
  5. 5.
    Fornaciari, W., Polentarutti, M., Sciuto, D., Silvano, C.: Power optimization of system-level address buses based on software profiling, In: Proceedings of International Conference on Hardware/Software Codesign (CODES), pp. 29–33 (2000)Google Scholar
  6. 6.
    Aghaghiri, Y., Fallah, F., Pedram, M.: ALBORZ: address level bus power optimization. In: Proceedings of International Symposium of Quality Electronic Design (ISQED), pp. 470–475 (2002)Google Scholar
  7. 7.
    Komatsu, S., Fujita, M.: Irredundant address bus encoding techniques based on adaptive codebooks for low power, In: Proceedings of the Conference on Asia South Pacific Design Automation (ASPDAC), pp. 9–14 (2003)Google Scholar
  8. 8.
    Stan, M.R., Burleson, W.P.: Limited-weight codes for low-power I/O, In: Proceedings of International Workshop on Low Power Design, Napa, CA, pp. 209–214, Apr 1994Google Scholar
  9. 9.
    Zhang, Y., Lach, J., Skadron, K., Stan, M.R.: Odd/even bus invert with two-phase transfer for buses with coupling. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 80–83 (2002)Google Scholar
  10. 10.
    Baek, K.H., Kim, K.W., Kang, S.M.: A low energy encoding technique for reductionof coupling effects in SOC interconnects. In: Proceedings of 43rd IEEE Midwest Symposium Circuits and Systems, Lansing, MI, pp. 80–83, Aug 2000Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringSri Venkateswara UniversityTirupatiIndia

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