Efficient VLSI Implementation of CORDIC-Based Multiplier Architecture
Multipliers have always played an important role in the field of VLSI architectures. The speed latency, area, and cost are the main encounters in designing a processor. Multiplication process takes a large amount of time and hence tries to reduce the speed of the processor. In this paper, an effort has been made to reduce the latency of a processor by implementing a multiplier less architecture. Volder introduced the CORDIC algorithm for computing trigonometric relationships. Using CORDIC, multiplier-less architectures can be obtained. The analysis is carried out using Xilinx ISE Design suite 14.2.
KeywordsCORDIC Analog resolver Vedic
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