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FPGA-Based Novel Speech Enhancement System Using Microphone Activity Detector

  • Tanmay Biswas
  • Shuvadeep Bhattacharjee
  • Sudhindu Bikash Mandal
  • Debasri Saha
  • Amlan Chakrabarti
Chapter
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 897)

Abstract

In this paper, we have proposed field-programmable gate array (FPGA) based design and implementation of a novel speech enhancement system, which can work for a single microphone device as well as that of a dual microphone device providing background noise immunity. We proposed a microphone activity detector (MAD), which detects the presence of single or dual microphone scenario. After detecting the microphones, multiband spectral subtraction technique enhances the speech signal from different background noisy surrounds. We have implemented our proposed design in Spartan 6 LX45 FPGA using Xilinx system generator tools. The evaluation of the quality of speech of enhanced signal and its correctness of MAD to detect the single or dual microphone system implies that our proposed hardware can work as a proper embedded component for hardware-based execution for speech enhancement.

Keywords

Time delay estimation Speech enhancement Field-programmable gate array Digital signal processor Multiband spectral subtraction 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Tanmay Biswas
    • 1
  • Shuvadeep Bhattacharjee
    • 1
  • Sudhindu Bikash Mandal
    • 1
  • Debasri Saha
    • 1
  • Amlan Chakrabarti
    • 1
  1. 1.A. K. Choudhury School of Information TechnologyUniversity of CalcuttaKolkataIndia

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