Design of High-Gain CG–CS 3.1–10.6 GHz UWB CMOS Low-Noise Amplifier

  • Dheeraj Kalra
  • Manish KumarEmail author
  • Abhay Chaturvedi
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 524)


A high-gain low-power CMOS low-noise amplifier is simulated using TSMC 0.18-µm CMOS technology. The cascade topology is used to get the high-gain and low-noise figure value. The source degeneration technique is used for the wideband matching. The circuit is simulated for 3.1–10.6 GHz in ultawideband. The simulated results show the maximum gain of 21.574 dB at 6.378 GHz and positive gain maintained during the entire frequency range. The highest noise figure value is 4.311 dB at 7.662 GHz, and the lowest value is 2.477 dB at 3.1 GHz. The matching circuit at input and output terminals shows the input return loss of 22.262 dB at 10.38 GHz, while the output return loss of 30.936 dB at 4.1 GHz. The circuit is simultaed at 1.2 V which draws the power consumption of 17.734 mW. The designed circuit shows the optimum value of gain, noise figure, matching and power consumption.


Low-Noise amplifier Noise figure S parameters 


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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.GLA UniversityMathuraIndia

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