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Low Power SAR ADC Based on Charge Redistribution Using Double Tail Dynamic Comparator

  • Sugandha Yadav
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 524)

Abstract

In this paper I have designed a low power SARADC based on charge redistribution. In the proposed design, I have designed a successive approximation register ADC using low power double tail dynamic comparator with control transistors (MC1 & MC2). The peculiar advantage of low power double tail dynamic comparator with control transistor (MC1 & MC2) is that the power consumption is reduced by three times as compared with the existing low power double tail dynamic comparator. The proposed comparator having the power consumption 58 µW can be operated at maximum frequency 16 MHz. Best efforts has been made to design an efficient SAR and control unit in the proposed design. In this 4-bit SAR ADC which can be operated at clock frequency of 16.5 MHz and having sampling frequency of 3.3 MHz is designed. The power consumption of the proposed circuit is 113 µW. In the paper quantization noise, SNR, SNDR and ENOBs are also obtained which are better in performances than existing ADCs.

Keywords

SAR ADC Charge redistribution Quantization noise Double tailed dynamic comparator SNR SNDR and ENOBs 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.School of VLSI Design & Embedded SystemNational Institute of Technology KurukshetraKurukshetraIndia

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