Advertisement

Analyzing the Complexity of Loop Shifting for Optimization of Matrix-Multiplication Process for System Having One Level Cache

  • Yogesh Singh RathoreEmail author
  • Dharminder Kumar
  • Kavita Saxena
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 755)

Abstract

Although the use of Matrix-Multiplication is very extensive in research. In our paper it is being used for optimization in case of level one cache memory. Initially Open-MP (OMP) is used, followed by various optimizing techniques. Finally the results of Matrix-Multiplication are verified by the mathematical proof in terms of complexity.

Keywords

Open-MP Cache Optimization Cache conscious Nested loops 

References

  1. 1.
    Compunity. The community of OpenMP users, researchers tool developers and provider website (2006). http://www.compunity.org/
  2. 2.
    Hammond, L., Nayfeh, B.A., Olukotun, K.: A single-chip multiprocessor. Computer 30(9), 79–85 (1997)Google Scholar
  3. 3.
    Jerraya, A., Tenhunen, H., Wolf, W.: Guest editors’ introduction: multiprocessor systems-on-chip. Computer l38(7), 36–40 (2005)Google Scholar
  4. 4.
    Ayguade, E., Copty, N., Duran, A., Hoeflinger, J., Lin, Y., Zhang, G.: A proposal for task parallelism in OpenMP. In: Proceedings of the 3rd International Workshop on OpenMP, June 2006Google Scholar
  5. 5.
    Zhong, H., Lieberman, S.A., Mahlke, S.A.: Extending multicore architecture to exploit hybrid parallelism in single thread applications. HPCA 25–36 (2007)Google Scholar
  6. 6.
    Dally, W.J., Lacy, S.: VLSI architecture: past, present, and future. In: ARVLSI ’99: Proceedings of the 20th Anniversary Conference on Advanced research in VLSI, p. 232. IEEE Computer Society, Washington, DC, USA (1999)Google Scholar
  7. 7.
    Kumar, S., Hughes, C.J., Nguyen, A.: Carbon: architectural support for fine-grained parallelism on chip multiprocessors. In: ISCA ’07: Proceedings of the 34th Annual International Symposium on Computer Architecture, pp. 162–173. ACM, New York, NY, USA (2007)Google Scholar
  8. 8.
    IOSR Journal of Engineering (IOSRJEN) www.iosrjen.org ISSN (e): 2250–3021, ISSN (p): 2278–8719 Vol. 04, Issue 01 (January. 2014), ||V3|| PP 56–59
  9. 9.
    IOSR Journal of Engineering (IOSRJEN) www.iosrjen.org ISSN (e): 2250–3021, ISSN (p): 2278–8719 Vol. 04, Issue 03 (March. 2014), ||V1|| PP 19–22
  10. 10.
  11. 11.
    Bousias, K., Hasasneh, N., Jesshope, C.: Instruction level parallelism through micro threading- a scalable approach to chip multiprocessors. Comput. J. 49(2), 211–233 (2006)Google Scholar
  12. 12.
    Rodrigues, A., Murphy, R., Kogge, P., Underwood, K.: Characterising a new class of threads in scientific applications for high end super computers. In: ICS ’04: proceedings of the 18th Annual International Conference on Super Computing, pp. 164–174. ACM, New York, NY, USA (2004)Google Scholar
  13. 13.
    Frigo, M., Leiserson, C.E., Randall, K.H.: The implementation of the Clik-5 multithreaded language. SIGPLAN Not. 33(5), 212–223 (1998)CrossRefGoogle Scholar
  14. 14.
    Buluc, A., Gilbert, J.R.: Challenges and advances in parallel sparce Matrix-Matrix-Multiplication. In: Proceedings of 37th International Conference on Parallel Processing ICPP’08, Portland, Sept 2008Google Scholar
  15. 15.
    Alonso, P., Reddy, R., Lastovetsky, A.: Experimental study of six different implementations of parallel Matrix-Multiplications on Hetrogenous Computational Clusters of Multi-core processors. In: Proceedings of Parallel, Distributed and Network Based Processing (PDP), Pisa, Feb. 2010Google Scholar
  16. 16.
    Ohshima, S., Kise, K., Katagiri, T., Yuba, T.: Parallel processing of matrix-multiplication in a CPU and GPU heterogeneous environment. High Perform. Comput. Computat. Sci.-VECPAR (2006)Google Scholar
  17. 17.
    Gorder, P.F.: Multi-Core processors for science and engineering. Comput. Sci. Engg. 9(2), 3–7 (2007).  https://doi.org/10.1109/mcse.2007.35

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Yogesh Singh Rathore
    • 1
    Email author
  • Dharminder Kumar
    • 2
  • Kavita Saxena
    • 1
  1. 1.Mewar UniversityChittorgarhIndia
  2. 2.Guru Jambheshwar University of Science & TechnologyHissarIndia

Personalised recommendations