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Reversible Code Converters Based on Application Specific Four Variable Reversible Gates

  • Sanjoy Banerjee
  • Abhijit Kumar Pal
  • Mahamuda Sultana
  • Diganta SenguptaEmail author
  • Abhijit Das
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 755)

Abstract

The rising research in reversible logic, estimating it to be latent alternative for CMOS, has paved the way for several proposals for reversible logic synthesis. Application oriented reversible circuit designs are witnessed in almost every aspect of digital communication. It is this very interest that the present study proposes binary to gray code converters and vice versa as two independent four variable reversible gates. The converters have been conceptualized as four variable reversible gates having potential to realize efficient parity generator/checker circuits exhibiting better peer comparison results. Hence the work in this paper may find acceptance in reversible cryptography as well as XOR intensive operations in image processors. Also by virtue of definition, reversibility supports lossless communication as information loss is arrested in subsequent stages of information transfer in a reversible function.

References

  1. 1.
    Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)MathSciNetCrossRefGoogle Scholar
  2. 2.
    Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Develop. 17, 525–532 (1973)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Lent, C., Tougaw, P., Porod, W., Bernstein, G.: Quantum cellular automata. Nanotechnology 4(1), 49–57 (1993)CrossRefGoogle Scholar
  4. 4.
    Sultana, M., Prasad, M., Roy, P., Sarkar, S., Das, S., Chaudhuri, A.: Comprehensive quantum analysis of existing four variable reversible gates. In: 2017 Devices for Integrated Circuit (DevIC), pp. 116–120. IEEE, Kolkata (2017)Google Scholar
  5. 5.
    Toffoli, T.: Reversible Computing. Tech Memo MIT/LCS/TM-151. MIT Lab for Computer Science (1980)Google Scholar
  6. 6.
    Fredkin, E., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21, 219–253 (1982)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Feynman, R.: Quantum mechanical computers. Opt. News 11, 11–20 (1985)CrossRefGoogle Scholar
  8. 8.
    Peres, A.: Reversible logic and quantum computers. Phys. Rev. A 32(6), 3266–3276 (1985)MathSciNetCrossRefGoogle Scholar
  9. 9.
    Maslov, D., Dueck, G., Miller, D.: Synthesis of Fredkin–Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. VLSI Syst. 13(6), 765–769 (2005)CrossRefGoogle Scholar
  10. 10.
    Vasudevan, D., Lala, P., Di, J., Parkerson, J.: Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2), 406–414 (2006)CrossRefGoogle Scholar
  11. 11.
    Thapliyal, H., Srinivas, M.: Novel reversible ‘TSG’ Gate and its application for designing components of primitive reversible/quantum ALU. In: Fifth International Conference on Information, Communications and Signal Processing (2005)Google Scholar
  12. 12.
    Maity, G., Maity, S.: Implementation of HNG using MZI. In: Third International Conference on Computing Communication & Networking Technologies (ICCCNT), pp. 1–6 (2012)Google Scholar
  13. 13.
    Sengupta, D., Sultana, M., Chaudhuri, A.: Realization of a novel reversible SCG Gate and its application for designing parallel adder/subtractor and match logic. Int. J. Comput. Appl. 31(9), 30–35 (2011)Google Scholar
  14. 14.
    James, R., Jacob, K., Sasi, S.: Design of compact reversible decimal adder using RPS gates. In: World Congress on Information and Communication Technologies (WICT), pp. 344–349 (2012)Google Scholar
  15. 15.
    Haghparast, M., Navi, K.: A Novel reversible full adder circuit for nanotechnology based systems. J. Appl. Sci. 7(24), 3995–4000 (2007)CrossRefGoogle Scholar
  16. 16.
    Haghparast, M., Navi, K.: A novel reversible BCD adder for nanotechnology based systems. Am. J. Appl. Sci. 5(3), 282–288 (2008)CrossRefGoogle Scholar
  17. 17.
    Islam, M., Rahman, M., Begum, Z.: Fault tolerant reversible logic synthesis: carry look-ahead and carry-skip adders. In: International Conference on Advances in Computational Tools for Engineering Applications, ACTEA ’09, pp. 396–401 (2009)Google Scholar
  18. 18.
    Rashmi, S., Umarani, T., Shreedhar, H.: Optimized reversible montgomery multiplier. Int. J. Comput. Sci. Inf. Technol. 2(2), 701–706 (2011)Google Scholar
  19. 19.
    Arun, M., Saravanan, S.: Reversible Arithmetic Logic Gate (ALG) for quantum computation. Int. J. Intell. Eng. Syst. 6(3), 1–9 (2013)Google Scholar
  20. 20.
    Biswas, A., Hasan, M., Chowdhury, A., Babu, H.: Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectron. J. 39(12), 1693–1703 (2008) (Elsevier)Google Scholar
  21. 21.
    Biswas, P., Gupta, N., Patidar, N.: Basic reversible logic gates and it’s QCA implementation. Int. J. Eng. Res. Appl. 4(6), 12–16 (2014)Google Scholar
  22. 22.
    Shukla, V., Singh, O., Mishra, G., Tiwari, R.: Application of CSMT gate for efficient reversible realization of binary to gray code converter circuit. In: 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON), pp. 1–6 (2015)Google Scholar
  23. 23.
    Bhagyalakshmi, H., Venkatesha, M.: Design of a multifunction BVMF reversible logic gate and its applications. Int. J. Comput. Appl. 32(3), 0975–8887 (2011)Google Scholar
  24. 24.
    Sultana, M., Chaudhuri, A., Sengupta, D., Chaudhuri, A.: Logic design and quantum mapping of a novel four variable reversible s2c2 gate. In: Nature, S., (ed.): CSI 2017—52nd Annual Convention of Computer Society of India, Kolkata (2018) (in Press)Google Scholar
  25. 25.
    Chaudhuri, A., Sultana, M., Sengupta, D., Chaudhuri, A.: A novel reversible two’s complement gate (TCG) and its quantum mapping. In: 2017 Devices for Integrated Circuit (DevIC), pp. 252–256. IEEE, Kolkata (2017)Google Scholar
  26. 26.
    Arabzadeh, M., Saeedi, M.: RCViewer+: A viewer/analyzer for reversible and quantum circuits (2008–2013, version 2.5)Google Scholar
  27. 27.
    Saravanan, M., Manic, K.S.: Energy efficient code converters using reversible logic Gates. In: Proceedings of 2013 International Conference on Green High Performance Computing, India, Mar 2013Google Scholar
  28. 28.
    Kamani, K., Koneti, S., Bollampalli, U., Shankara, S.: Energy efficient reversible logic design for code converters. Int. J. Res. Appl. 1(3), 132–136 (2014)Google Scholar
  29. 29.
    Haghparast, M., Hajizadeh, M., Bashiri, R.: On the synthesis of different nanometric reversible converters. Middle-East J. Sci. Res. 7(5), 715–720 (2011)Google Scholar
  30. 30.
    Das, J., De, D.: Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication. Front. Inf. Technol. Electron. Eng. 3, 224–236 (2016–17)Google Scholar
  31. 31.
    Gayathri, S., Ananthalakshmi, A.: Design and implementation of efficient reversible even parity checker and generator. In: International Conference on Science Engineering and Management Research (ICSEMR), pp. 1–4 (2014)Google Scholar
  32. 32.
    Mustafa, M., Beigh, M.: Design and implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count. Indian J. Pure Appl. Phys. 51, 60–66 (2013)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Sanjoy Banerjee
    • 1
  • Abhijit Kumar Pal
    • 1
  • Mahamuda Sultana
    • 2
  • Diganta Sengupta
    • 3
    Email author
  • Abhijit Das
    • 4
  1. 1.Future Institute of Engineering & ManagementKolkataIndia
  2. 2.Techno India College of TechnologyKolkataIndia
  3. 3.Techno India – BatanagarKolkataIndia
  4. 4.RCC Institute of Information TechnologyKolkataIndia

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