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Adept-Disseminated Arithmetic-Based Discrete Cosine Transform

  • K. B. Sowmya
  • Jose Alex Mathew
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 755)

Abstract

Disseminated arithmetic (DA) based construction of DCT for less circuit cost and less power consumption is presented here. Using disseminated arithmetic-less number of additions is used to the Discrete Cosine Transform by exploiting the time property of the DCT. The planned One-D DCT architecture is implemented on the Xilinx FPGA. The document describes the design of two-dimensional discrete cosine transform (DCT) which is widely used in image and video compression algorithms. The intention of this paper is to design a totally parallel distributed arithmetic (DA) architecture for two-dimensional DCT. DCT requires great amount of statistical computations including addition and multiplication. Multipliers are finally avoided in the projected design as an alternative DA-Based ROM and ROM accumulators are used, thereby rich-throughput DCT designs have been taken to fit the requirements of instantaneous applications. Disseminated arithmetic is a method of adaptation at bit stream for SOP or vector dot product to partition the multiplications. The speed is increased in the wished-for design with the fully corresponding approach. In this work, existing DA architecture for two-dimensional DCT and the proposed area efficient fully parallel DA architecture for two-dimensional DCT are realized. The modeling and synthesizing is performed using Xilinx ISE.

Keywords

FPGA (Field programmable gate arrays) Two-dimensional discrete cosine transform (two-dimensional DCT) Disseminated arithmetic (DA) 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.R V College of EngineeringBengaluruIndia
  2. 2.Srinivas Institute of TechnologyMangaluruIndia

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