Design of High Performance Compute Node for Belle II Pixel Detector Data Acquisition System
Belle II Pixel Detector (PXD) is a new designed silicon pixel detector on Belle II upgrade. It generate up to 240 Gbit data per second. With the help of Silicon Vertex Detector (SVD) and other detectors, PXD data will reduce to 1/30. High Performance Compute Node (CN) is used as the central board of PXD Data Acquisition (DAQ) System. Intelligent Platform Management Controller and Module Management Controller (IPMC/MMC) are used to monitor power consumption, temperature and firmware download. Final version of Compute Node is finished in 2015 and successfully joined beam test with PXD, SVD, frond-end readout part and High Level Trigger (HLT) in DESY in Jan. 2017.
KeywordsPXD Compute Node IPMC/MMC
This project has been supported by National Natural Science Foundation of China (11435013, 11461141011, 11405196).
- 1.Doležal, Z., et al.: Belle II Technical Design Report. High Energy Accelerator Research Organization, Tsukuba (2010)Google Scholar
- 2.Doležal, Z., Kiesling, C., et al.: The PXD Whitebook, July 2012Google Scholar
- 3.PICMG 3.0 R2.0 AdvancedTCA Base Specification ECN-002 May 26, 2006Google Scholar
- 4.Zhao, J., et al.: A general xTCA compliant and FPGA based data processing building blocks for trigger and data acquisition system. Presented at the 19th IEEE-NPSS Real Time Conference, Nara, Japan, May 2014Google Scholar
- 5.Sun, D., Liua, Z., Zhao, J., Xu, H.: Belle2Link: a global data readout and transmission for Belle II experiment at KEK. Phys. Procedia 37(0), 1933–1939 (2012). https://doi.org/10.1016/j.phpro.2012.01.036
- 6.Lange, S.: ONSEN phase 2 readiness. In: 27th B2GM, 19–23 June 2017. KEK, TsukubaGoogle Scholar