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Study of Front-End High Speed Readout Based on JESD204B

  • Zhao Liu
  • Zhen-An Liu
  • Jing-zhou Zhao
  • Wen-xuan Gong
  • Li-bo Cheng
  • Peng-cheng Cao
  • Jia Tao
  • Han-jun Kou
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 212)

Abstract

This paper describes a high-speed data readout method for a large-scale front-end electronics in the JESD204B protocol-like transmission protocol implemented in a FPGA, in addition to a reading out for a commercial ADC. A prototype board including analog signal processing, digitization, digital processing and control in FPGA, and data transmission has been designed and together with a lab designed data receiver board, a demo system has been setup for this study of new method. The JESD204B protocol is implemented in FPGA, which is compared and verified by the commercial ADC output and the test results are showed satisfactory.

Keywords

ADC Data readout JESD204B 

Notes

Acknowledgments

This project has been Supported by National Natural Science Foundation of China (Grant No. 11435013) and Ministry of Science and Technology of the People’s Republic of China (Grant No. 2016YFA0400104).

References

  1. 1.
    JEDEC Standard: Serial Interface for Data Converters JESD204B.01Google Scholar
  2. 2.
    Lin, H.-C.: Research on self-trigger front-end unit for low frequency radio detection. Ph.D., thesisGoogle Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Zhao Liu
    • 1
    • 2
  • Zhen-An Liu
    • 1
  • Jing-zhou Zhao
    • 1
  • Wen-xuan Gong
    • 1
  • Li-bo Cheng
    • 1
    • 2
  • Peng-cheng Cao
    • 1
    • 2
  • Jia Tao
    • 1
    • 2
  • Han-jun Kou
    • 1
    • 2
  1. 1.State Key Laboratory of Particle Detection and ElectronicsInstitute of High Energy Physics, CAS and University of Science and Technology of ChinaBeijingChina
  2. 2.University of Chinese Academy of SciencesBeijingChina

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