Study of Front-End High Speed Readout Based on JESD204B
This paper describes a high-speed data readout method for a large-scale front-end electronics in the JESD204B protocol-like transmission protocol implemented in a FPGA, in addition to a reading out for a commercial ADC. A prototype board including analog signal processing, digitization, digital processing and control in FPGA, and data transmission has been designed and together with a lab designed data receiver board, a demo system has been setup for this study of new method. The JESD204B protocol is implemented in FPGA, which is compared and verified by the commercial ADC output and the test results are showed satisfactory.
KeywordsADC Data readout JESD204B
This project has been Supported by National Natural Science Foundation of China (Grant No. 11435013) and Ministry of Science and Technology of the People’s Republic of China (Grant No. 2016YFA0400104).