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Estimation of Sampling Time Offsets in an N-Channel Time-Interleaved ADC Network Using Differential Evolution Algorithm and Correction Using Fractional Delay Filters

  • M. V. N. Chakravarthi
  • Bhuma Chandramohan
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 748)

Abstract

Higher sampling rates are essential in any communication system at present due to the demand for higher data rates. Such high sampling rates can be achieved with time-interleaved analog-to-digital converters (TI-ADCs). Even though TI-ADCs are faster, the sampling time offset is a setback. The sampling time offsets present in ADCs generate nonuniform samples. In the reconstruction process, these nonuniform samples might produce an erroneous signal. In this work, estimation of these sampling time offsets is performed using differential evolution algorithm. The proposed algorithm efficiently detects the sampling time offsets with minimum number of iterations. The estimated sampling time offsets are used to reconstruct the signal using fractional delay filters. Performance of the proposed algorithm is tested by considering various signals, i.e., speech signal, sinusoidal, and amplitude modulated signal (AM). Signal-to-noise ratio (SNR) and signal-to-noise distortion ratio (SNDR) are calculated for the signals. The results are compared with the existing works and noteworthy improvement with the proposed algorithm is demonstrated.

Keywords

Time-interleaved ADC Sampling time offset Differential evolution Fractional delay filter 

References

  1. 1.
    Beydoun, Ali, Nguye, Van-Tam, Naviner, L., Loumeau, P.: Optimal digital reconstruction and calibration for multichannel time interleaved ADC based on comb-filters. Int. J. Electron. Commun. 67, 329–339 (2013)CrossRefGoogle Scholar
  2. 2.
    Chen, Hongmei, Pan, Yunsheng, Yin, Yongsheng, Lin, Fujiang: All-digital background calibration technique for timing mismatch of time interleaved ADCs. Integr. VLSI J. 57, 45–51 (2017)CrossRefGoogle Scholar
  3. 3.
    Li, D., Zhu, Z., Zhang, L., Yang, Y.: A background fast convergence algorithm for timing skew in time-interleaved ADCs. Microelectron. J. 47, 45–52 (2015)Google Scholar
  4. 4.
    Benwei, Xu, Chiu, Yun: Comprehensive background calibration of time-interleaved analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 62, 1306–1314 (2015)CrossRefGoogle Scholar
  5. 5.
    Prashanth, D., Seung, H: A sampling clock skew correction technique for time-interleaved SAR ADCs. In: GLVLSI’16 Proceedings of the 26th edition on Great Lakes Symposium on VLSI, pp. 129–132 (2016)Google Scholar
  6. 6.
    Liu, S.J., Qi, P.P., Wang, J.S., Zhang, M.H., Jiang, W.S.: Adaptive calibration of channel mismatches in time-interleaved ADCs based on equivalent signal recombination. IEEE Trans. Instrum. Meas. 63, 277–286 (2014)CrossRefGoogle Scholar
  7. 7.
    Qin, J., Liu, G.M., Guo, M.G.: Adaptive calibration method for timing mismatch error in time-interleaved ADC system. Chin. J. Sci. Instrum. 34, 2371–2375 (2013)Google Scholar
  8. 8.
    Yao, Y., Yan, B., Li, G., Lin, S.: Adaptive blind compensation of timing mismatches in four-channel time-interleaved ADCs. In: 2013 International Conference on Communications, Circuits and Systems (ICCCAS), pp. 232–234 (2013)Google Scholar
  9. 9.
    Carvajal, W., Van Noije, W.: Time-interleaved pipeline ADC design: a reconfigurable approach supported by optimization. In: SBCCI Proceedings of the 24th Symposium on Integrated Circuits And Systems Design, pp. 17–22 (2011)Google Scholar
  10. 10.
    Camarero, D., Naviner, J.-F.: Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters. In: SBCCI’04 Proceedings of the 17th Symposium on Integrated Circuits and System Design, pp. 228–232 (2004)Google Scholar
  11. 11.
    Jamal, S.M., Fu, D., Singh, M.P., Hurst, P.J., Lewis, S.H.: Calibration of sample-time error in a two-channel time- interleaved analog-to-digital converter. IEEE Trans. Circuits Syst. I 51, 130–139 (2004)Google Scholar
  12. 12.
    Jin, H., Lee, E.K.F.: A digital-background calibration technique for minimizing timing-error effects in TI-ADCs. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47, 603–613 (2000)Google Scholar
  13. 13.
    Vaidyanathan, P.P.: Multirate Systems and Filter Banks. Pearson, India, (1993)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.Department of Electronics & Communication EngineeringAcharya Nagarjuna UniversityGunturIndia
  2. 2.Department of Electronics & Communication EngineeringBapatla Engineering CollegeBapatlaIndia

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