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A Low-Voltage Distinctive Source-Based Sense Amplifier for Memory Circuits Using FinFETs

  • Arti Ahir
  • Jitendra Kumar Saini
  • Avireni Srinivasulu
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 670)

Abstract

SRAM is the key element used in digital circuits. It is also used as a cache memory in computers, automatic modern equipment like mobile phones, modern appliances, digital calculators, digital cameras, so that the requirements of high-speed advanced memory or embedded memory lead to the development of low-voltage SRAMs. The paper has introduced the design and simulation of the distinctive source-based sense amplifier which is a peripheral circuit for static random access memory (SRAM) that has to amplify the data which is present on the bit lines during the read operation. Simulation of the proposed design has been implemented using 20 nm FinFET technology on the Cadence Virtuoso Tool with a supply voltage of +0.4 V. The main advantages from the proposed design circuit are less power consumption and display of minimum sense delay in sensing the data from SRAM when compared to the existing design circuit. A comparison is drawn between the proposed circuit and the existing design circuit.

Keywords

FinFET Delay Low voltage Sense amplifier SRAM 

References

  1. 1.
    Jaydeep, P. K., John, K., Kyung-Hoae, K., Satyanand, N., Zheng, Guo., Eric, K., Kevin, Z.: 5.6 Mb/mm2 1R1 W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE Journal of Solid-State Circuits. vol. 52, issue. 1, pp. 229–239, (2017).  https://doi.org/10.1109/jssc.2016.2607219.
  2. 2.
    Innocent Agbo., Mottaqiallah Taouil., Daniël Kraak., Said Hamdioui., Halil Kükner., Pieter Weckx., Praveen Raghavan., Francky Catthoor.: Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. vol. PP, issue: 99, pp. 1–11, (2017).Google Scholar
  3. 3.
    Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, and Xiaoyang Zeng.: Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Transactions on circuits and systems-II, Express Briefs, vol. 63, no. 7, pp. 643–647, (2016).Google Scholar
  4. 4.
    Balakrishna, K., Srinivasulu, A., Sarada, M.: 7-T single end and 8-T differential dual-port SRAM memory cells. IEEE Conference on Information and Communication Technologies (IEEE ICT-2013), Kumaracoil, India, Apr 11-12, pp. 1243–1246, (2013).  https://doi.org/10.1109/cict.2013.6558291.
  5. 5.
    M. R. Garg, Anu Tonk, “A study of different types of voltage & current sense amplifiers used in SRAM”, International Journal of Advanced Research in Computer and Communication Engineering, vol. 4, Issue. 5, pp. 30–35, (2015).Google Scholar
  6. 6.
    Ya-Chun Lai., Shi-Yu Huang.: A Resilient and Power Efficient Automatic Power down Sense Amplifier for SRAM Design. IEEE Trans. on Circuits & Systems, vol. 55, no. 10, pp. 1031–1035, (2008).Google Scholar
  7. 7.
    Tiffany Moy., Liechao Huang., Warren Rieutort-Louis., Can Wu., Paul Cuff., Sigurd Wagner., James C. Sturm., Naveen, V:. An EEG Acquisition and Biomarker-Extraction System Using Low-Noise-Amplifier and Compressive-Sensing Circuits Based on Flexible, Thin-Film Electronics. IEEE Journal of Solid-State Circuits, vol. 52, Issue. 1, pp. 309–321, (2017).  https://doi.org/10.1109/jssc.2016.2598295.
  8. 8.
    Yiping Zhang., Ziou Wang.,. Canyan Zhu., Lijun Zhang.: 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. vol. PP, issue. 99, pp. 1–7, (2017).Google Scholar
  9. 9.
    Sivakumari, K., Srinivasulu, A., Reddy, V.V.: A High Slew Rate, Low Voltage CMOS Class-AB Amplifier. IEEE Applied Electronics International Conference (IEEE AEIC-14), Pilsen, Czech Republic, Sep 9-10, 2014, pp. 267–270, (2014).  https://doi.org/10.1109/ae.2014.7011717.
  10. 10.
    Chong, K. S., Ho, W-G., Lin, T., Gwee, B-H., Joseph, S. Ch.: Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 25, issue. 25, pp. 402–415, (2017).  https://doi.org/10.1109/tvlsi.2016.2583118.
  11. 11.
    Taehui Na., S. Woo., J. Kim., H. Jeong., S. Jung.: Comparative Study of Various Latch-Type Sense Amplifiers. IEEE Trans. On VLSI Systems, vol. 22, no. 2, pp. 425–429, (2014).Google Scholar
  12. 12.
    Wicht, B., Nirschl, T., Schmitt-Landsiede, D.: Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, (2004).Google Scholar
  13. 13.
    Xue Lin, Yanzhi Wang and Massoud Pedram.: Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime. in Proc. IEEE 15th International Symposium on Quality Electronic Design, pp. 341–348, (2014).Google Scholar
  14. 14.
    Nagateja, T., Rao, T. V., Srinivasulu, A.: Low Voltage, High Speed FinFET Based 1-BIT BBL-PT Full Adders. in proc. IEEE International Conference on Communication and Signal Processing (IEEE ICCSP’ 15), Melmaruvathur, Tamilnadu, India, April 2-4, (2015), pp. 1247–1251.Google Scholar
  15. 15.
    Chandankhede, R. D., Acharya, D. P., Patra, P.: Design of high speed Sense amplifier for SRAM. in proc. of International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), 8-10 May 2014, pp. 340–343.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Arti Ahir
    • 1
  • Jitendra Kumar Saini
    • 1
  • Avireni Srinivasulu
    • 2
  1. 1.Department of E.C.EBirla Institute of Technology, MesraJaipur CampusIndia
  2. 2.Department of Electronics and Communication Engineering, School of EngineeringJECRC UniversityJaipurIndia

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