Adiabatic SRAM Cell and Array

  • Ayon Manna
  • V. S. Kanchana BhaaskaranEmail author
Part of the Studies in Computational Intelligence book series (SCI, volume 771)


A new SRAM cell with better leakage control and enhanced memory retention capability is proposed. The memory array configured using the proposed SRAM cell has all its word lines and bit lines driven adiabatically using differential cascode and pre-resolved adiabatic logic (DCPAL), and it operates as a buffer for the memory array. This paper demonstrates how one of major concerns, namely, the VT variation can be controlled by modifying the ground-line and power-line voltage of the SRAM cell. The designs are implemented using 45-nm technology models operating at a supply voltage of 0.8 V.


SRAM cell design Adiabatic logic circuit Leakage current in memory Adiabatic buffer circuits 


  1. 1.
    Kanchana Bhaaskaran, V.S. 2011. Energy recovery performance of quasi adiabatic circuits using lower technology nodes. In India international conference on power electronics 2010 (IICPE2010), 1–7, New Delhi.Google Scholar
  2. 2.
    Nakata, S., T. Kusumuto, M. Miyama, and Y. Matsuda. 2009. Adiabatic SRAM with a large margin of VT variation by controlling the cell power line and word line voltage. In Proceedings ISCAS digest, 393–396.Google Scholar
  3. 3.
    Kanchana Bhaaskaran, V.S., S. Salivahanan, and D.S. Emmanuel. 2006. Semi-custom design of adiabatic adder circuits. In Proceedings of 19th international conference on VLSI design and embedded systems design, 745–748.Google Scholar
  4. 4.
    Hu, J., H. Li, and H. Dong. 2005. A low-power adiabatic register file with two types of energy-efficient line drivers. In 48th Midwest symposium on circuits and systems, 1753–1756.Google Scholar
  5. 5.
    Hu, J.P., X.Y. Feng, J.J. Yu, and Y.S. Xia. 2004. Low power dual transmission gate adiabatic logic circuits and design of SRAM. In 47th Midwest symposium on circuits and systems, 565–568.Google Scholar
  6. 6.
    Sudarshan, Patil, and V.S. Kanchana Bhaaskaran. 2017. Optimization of power and energy in FinFET based SRAM cell using adiabatic logic. In IEEE International conference on Nextgen Electronic Technologies: Silicon to software (ICNETS2). Chennai, 23–25 March 2017.Google Scholar
  7. 7.
    Dinesh Kumar, S., S.K. Noor Mahammad. 2015. A novel adiabatic SRAM cell implementation using split level charge recovery logic. In IEEE 19th international symposium on VLSI design and test (VDAT), 1–2.Google Scholar
  8. 8.
    Nakata, S., H. Suzuki, T. Kusumuto, S.I. Mutoh, H. Makino, M. Miyama, and Y. Matsuda. 2010. Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. In Proceedings of 2010 IEEE international symposium on circuits and systems, 2474–2477.Google Scholar

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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  1. 1.School of Electronics EngineeringVIT University ChennaiChennaiIndia

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