FPGA Implementation of OLS (32, 16) Code and OLS (36, 20) Code

  • Arghyadeep Sarkar
  • Jagannath Samanta
  • Amartya Barman
  • Jaydeb Bhaumik
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 470)

Abstract

Orthogonal Latin square (OLS) codes are one type of one-step majority logic decodable (OS-MLD) error correcting code. These codes provide fast and simple decoding procedure. The OLS codes are used for correcting multiple cell upsets (MCU) which occur in semiconductor memories due to radiation-induced soft errors. OLS codes are derived from Latin squares and can be efficiently implemented on reconfigurable architectures like field programmable gate arrays (FPGA). This paper describes the construction of OLS codes from their parity check matrices and the method for increasing the data block size by extending the original OLS code. Here, double error correcting OLS (32, 16) code and OLS (36, 20) code have been designed and implemented on SRAM-based Xilinx FPGA. The synthesis results of area and delay of the encoder and decoder blocks are also presented. It is observed that extending the OLS codes will result in significant overhead in terms of the overall available resources and the delay of the codec circuits.

Keywords

Error correcting code Orthogonal Latin square Memory Soft error FPGA 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2017

Authors and Affiliations

  • Arghyadeep Sarkar
    • 1
  • Jagannath Samanta
    • 2
  • Amartya Barman
    • 3
  • Jaydeb Bhaumik
    • 2
  1. 1.Jalpaiguri Government Engineering CollegeJalpaiguriIndia
  2. 2.Haldia Institute of TechnologyHaldiaIndia
  3. 3.WiproBangaloreIndia

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