Low Power Adder Circuit Based on Coupling Technique

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)

Abstract

Today’s technology is continuously scaling itself, thereby resulting in increasing density of the transistors leading to high power dissipation on the chip. Therefore, we need to reduce this power consumption of these circuits and make them more efficient. In this paper, we have introduced two transistors in the Static Energy Recovery Full adder circuit by twisted coupled technique to achieve the power reduction of the circuit. The circuitry proposed in this paper is intended to be operated at 1 V supply with 0.12 mW on 90 nm CMOS technology.

Keywords

Adders MOS SERF Low power 

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Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringASET, Amity UniversityNoidaIndia

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