Fat Tree NoC Design and Synthesis

  • Arpit Jain
  • Alok Kumar Gahlot
  • Rakesh Dwivedi
  • Adesh Kumar
  • Sanjeev Kumar Sharma
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)

Abstract

Network on chip (NoC) architecture is the promising solution over the limitations of bus-based system. The on-chip communication is addressed by several NoC topological structures and guarantees reliable, fast, and scalable design. The paper addresses the design of fat NoC tree topology that can process the intercommunication from top to root nodes. The tree NoC is indirect topology in which the routers are not dependent on the number of ports. The design is developed in Xilinx ISE 14.2 software with the help of VHDL language, and the design is targeted on Virtex-5 FPGA. The hardware parameters and timing values are estimated to support the functionality of the design.

Keywords

Interprocess communication Field-programmable gate array (FPGA) Fat tree network on chip (NoC) 

References

  1. 1.
    Andreas Hansson, Kees Goossens and Andrei Radulescu “A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic” Hindawi Publishing Corporation VLSI Design, pp 1–16, 2007.Google Scholar
  2. 2.
    Adesh Kumar, Piyush Kuchhal, Sonal Singhal “Network on Chip for 3D Mesh Structure with Enhanced Security Algorithm in HDL Environment” International Journal of Computer Applications (IJCA) Vol. 59– Number 17, pp 6–13, December 2012.Google Scholar
  3. 3.
    Bergamaschi RA, Cohn J “The A to Z of SoCs. In: Proceedings of the IEEE/ACM international conference on computer aided design (ICCAD)”, Yorktown Heights, pp 791–798, 2002.Google Scholar
  4. 4.
    C. Neeb, M.J. Thul, N. When, “Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders”, IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, pp 1766–1769, May 2005.Google Scholar
  5. 5.
    D. Wiklund, L. Dake Liu, “SoCBUS: switched network on chip for hard real time embedded systems,” in Parallel and Distributed Processing Symposium, pp. 8–9, April 2003.Google Scholar
  6. 6.
    David Atienzaa, Federico Angiolini, Srinivasan Murali, Antonio Pullinid, Luca Benini, Giovanni De Micheli, “Network-on-Chip design and synthesis outlook”, Integration, the VLSI journal Elsevier Vol. 41 pp 340–359, 2008.Google Scholar
  7. 7.
    Dally WJ, Towles B “Route packets, not wires: on-chip interconnection networks”. In: Proceedings of the design automation conference (DAC), Las Vegas, pp 684–689, 2001.Google Scholar
  8. 8.
    Lu R, Koh C-K “Samba-BUS: high performance BUS architecture for system-on-chips”. In: Proceedings of the IEEE/ACM international conference on computer aided design (ICCAD), San Jose, pp 8–12, 2003.Google Scholar
  9. 9.
    Erika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski Book “Reliability, Availability and Serviceability of Networks on Chip” Springer New York Dordrecht Heidelberg London, 2, pp (1–24), 2012.Google Scholar
  10. 10.
    Konstantinos Tatas, Kostas Siozios Dimitrios Soudris, Axel Jantsch Book Ch-1, Ch-2 “Designing 2D and 3D Network-on-Chip Architectures” Springer New York Heidelberg Dordrecht London, pp 1–45, 2014.Google Scholar
  11. 11.
    M. Jabbar, D. Houzet, “3D architecture implementation: a survey”, in IP Embedded System Conference (IP-SOC), pp. 1–5, 2011.Google Scholar
  12. 12.
    M. Dall’Osso, G. Biccari, L. Giovannini, D. Bertozzi, L. Benini, “Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs,” in International Conference on Computer Design (ICCD), pp. 45–48, 2012.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Arpit Jain
    • 1
  • Alok Kumar Gahlot
    • 1
  • Rakesh Dwivedi
    • 1
  • Adesh Kumar
    • 2
  • Sanjeev Kumar Sharma
    • 3
  1. 1.Department of Computer Science and Information TechnologyTeerthanker Mahaveer UniversityMoradabadIndia
  2. 2.Department of Electronics, Instrumentation and Control EngineeringUniversity of Petroleum and Energy Studies (UPES)DehradunIndia
  3. 3.Department of Computer Science & EngineeringJP Institute of Engineering & TechnologyMeerutIndia

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