Design of 2-Bit Vedic Multiplier Using PTL and CMOS Logic

  • Gaurav Bajaj
  • Kabir Grover
  • Anu Mehra
  • Sachin Kumar Rajput
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 624)

Abstract

The requirement of a high-speed multiplier is expanding. It is one of the most important hardware blocks in a processing system. A multiplier acts as a high delay block, and it also dissipates a lot of power. An ordinary processor requires more time and resources in multiplication operation. The proposed design of the 2-bit Vedic multiplier has been designed using pass transistor logic. The Vedic multiplier is the fastest, reliable, efficient, and low-power multipliers. By reducing the number of partial products, the delay also decreased and the system becomes faster. The design and the properties of this multiplier have been studied and performed using the Pyxis Schematic software (90 nm), and the power dissipation and delay have been compared with 2-bit multiplier using CMOS logic. The analysis is made for voltage range from 0.8 to 1.5 V.

Keywords

Vedic multiplier Pass transistor logic CMOS logic Power dissipation Delay 

References

  1. 1.
    Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, “Vedic Mathematics or Sixteen Simple Mathematical Formulae from the Veda, Delhi (1965)”, Motilal Banarsidas, Varanasi, India, 1986.Google Scholar
  2. 2.
    G. Ganesh Kumar, V. Charishma, “Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques”, International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012 1 ISSN 2250-3153.Google Scholar
  3. 3.
    Sushma R. Huddar, Sudhir Rao Rupanagudi, Kalpana M and Surabhi Mohan, “Novel High Speed Vedic Mathematics Multiplier using Compressors”, International Multi conference on Automation, Computing, Communication, Control and Compressed Sensing(iMac4s), 22–23 March 2013, Kottayam, ISBN: 978-1-46735090-7/13, pp.465–469.Google Scholar
  4. 4.
    M.E. Praramasivam, Dr. R.S. Sabeenian, “An Efficient Bit Reduction Binary Multiplication Algorithm using Vedic Methods”, IEEE, 2010.Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd. 2018

Authors and Affiliations

  • Gaurav Bajaj
    • 1
  • Kabir Grover
    • 1
  • Anu Mehra
    • 1
  • Sachin Kumar Rajput
    • 1
  1. 1.ASET, Amity University Uttar PradeshNoidaIndia

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