Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms

  • Vladimir Verstov
  • Vadim Shakhnov
  • Lyudmila Zinchenko
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 423)

Abstract

In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.

Keywords

VLSI Layout Double Pattering Parallel Algorithms High- Performance Computing Radiation Hardening 

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Copyright information

© IFIP International Federation for Information Processing 2014

Authors and Affiliations

  • Vladimir Verstov
    • 1
  • Vadim Shakhnov
    • 1
  • Lyudmila Zinchenko
    • 1
  1. 1.Bauman Moscow State Technical UniversityMoscowRussia

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