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A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement

  • Mudit Bhargava
  • Ken Mai
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8086)

Abstract

Achieving high reliability across environmental variations and over aging in physical unclonable functions (PUFs) remains a challenge for PUF designers. The conventional method to improve PUF reliability is to use powerful error correction codes (ECC) to correct the errors in the raw response from the PUF core. Unfortunately, these ECC blocks generally have high VLSI overheads, which scale up quickly with the error correction capability. Alternately, researchers have proposed techniques to increase the reliability of the PUF core, and thus significantly reduce the required strength (and complexity) of the ECC. One method of increasing the reliability of the PUF core is to use normally detrimental IC aging effects to reinforce the desired (or “golden”) response of the PUF by altering the PUF circuit characteristics permanently and hence making the PUF more reliable. In this work, we present a PUF response reinforcement technique based on hot carrier injection (HCI) which can reinforce the PUF golden response in short stress times (i.e., tens of seconds), without impacting the surrounding circuits, and that has high permanence (i.e., does not degrade significantly over aging). We present a self-contained HCI-reinforcement-enabled PUF circuit based on sense amplifiers (SA) which autonomously self-reinforces with minimal external intervention. We have fabricated a custom ASIC testchip in 65nm bulk CMOS with the proposed PUF design. Measured results show high reliability across environmental variations and accelerated aging, as well as good uniqueness and randomness. For example, 1600 SA elements, after being HCI stressed for 125s, show 100% reliability (zero errors) across ±20% voltage variations a temperature range of -20°C to 85°C.

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References

  1. 1.
    Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Silicon physical random functions. In: CCS 2002: Proceedings of the 9th ACM Conference on Computer and Communications Security, pp. 148–160. ACM, New York (2002)Google Scholar
  2. 2.
    Suh, G.E., Devadas, S.: Physical Unclonable Functions for Device Authentication and Secret Key Generation. In: Proceedings of 44th ACM/IEEE Design Automation Conference DAC 2007, pp. 9–14 (2007)Google Scholar
  3. 3.
    Lee, J.W., Lim, D., Gassend, B., Suh, G.E., van Dijk, M., Devadas, S.: A technique to build a secret key in integrated circuits for identification and authentication applications. In: Proceedings of Digest of Technical Papers VLSI Circuits 2004 Symp., pp. 176–179 (2004)Google Scholar
  4. 4.
    Lim, D., Lee, J.W., Gassend, B., Suh, G.E., van Dijk, M., Devadas, S.: Extracting secret keys from integrated circuits 13(10), 1200–1205 (2005)Google Scholar
  5. 5.
    Holcomb, D.E., Burleson, W.P., Fu, K.: Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers 58(9), 1198–1210 (2009)Google Scholar
  6. 6.
    Bhargava, M., Cakir, C., Mai, K.: Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses. In: Proceedings of IEEE Int Hardware-Oriented Security and Trust (HOST) Symp. (2010)Google Scholar
  7. 7.
    Bhargava, M., Cakir, C., Mai, K.: Comparison of Bi-stable and Delay-based Physical Unclonable Functions from Measurements in 65nm bulk CMOS. In: Custom Integrated Circuits Conference, CICC 2012. IEEE (September 2012)Google Scholar
  8. 8.
    Maes, R., Rozic, V., Verbauwhede, I., Koeberl, P., van der Sluis, E., van der Leest, V.: Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS. In: 2012 Proceedings of the ESSCIRC (ESSCIRC), pp. 486–489 (September 2012)Google Scholar
  9. 9.
    Yu, M.D., Devadas, S.: Secure and Robust Error Correction for Physical Unclonable Functions. IEEE Design & Test of Computers 27(1), 48–65 (2010)CrossRefGoogle Scholar
  10. 10.
    Maes, R., Van Herrewege, A., Verbauwhede, I.: PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator. In: Prouff, E., Schaumont, P. (eds.) CHES 2012. LNCS, vol. 7428, pp. 302–319. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  11. 11.
    Dodis, Y., Reyzin, L., Smith, A.: Fuzzy extractors: How to generate strong keys from biometrics and other noisy data. In: Cachin, C., Camenisch, J.L. (eds.) EUROCRYPT 2004. LNCS, vol. 3027, pp. 523–540. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  12. 12.
    Guajardo, J., Kumar, S.S., Schrijen, G.-J., Tuyls, P.: FPGA Intrinsic PUFs and Their Use for IP Protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 63–80. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  13. 13.
    Bösch, C., Guajardo, J., Sadeghi, A.-R., Shokrollahi, J., Tuyls, P.: Efficient Helper Data Key Extractor on FPGAs. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 181–197. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  14. 14.
    Yu, M.-D(M.), M’Raihi, D., Sowell, R., Devadas, S.: Lightweight and secure PUF key storage using limits of machine learning. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 358–373. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  15. 15.
    Guajardo, J., Kumar, S.S., Schrijen, G.J., Tuyls, P.: Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection. In: Proceedings of Int. Conference Field Programmable Logic and Applications FPL 2007, pp. 189–195 (2007)Google Scholar
  16. 16.
    Bhargava, M., Cakir, C., Mai, K.: Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. In: 2012 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 25–30 (June 2012)Google Scholar
  17. 17.
    Vivekraja, V., Nazhandali, L.: Circuit-level techniques for reliable physically uncloneable functions. In: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2009, pp. 30–35 (July 2009)Google Scholar
  18. 18.
    Pobegen, G., Aichinger, T., Nelhiebel, M., Grasser, T.: Understanding temperature acceleration for NBTI. In: 2011 IEEE International Electron Devices Meeting (IEDM), pp. 27.3.1 –27.3.4 (December 2011)Google Scholar
  19. 19.
    Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., Vrudhula, S.: Predictive Modeling of the NBTI Effect for Reliable Design. In: Custom Integrated Circuits Conference, CICC 2006, pp. 189–192. IEEE (September 2006)Google Scholar
  20. 20.
    Miyaji, K., Suzuki, T., Miyano, S., Takeuchi, K.: A 6t sram with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. In: 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 232–234 (Feburary 2012)Google Scholar
  21. 21.
    Agarwal, K., Nassif, S.: Characterizing Process Variation in Nanometer CMOS. In: Proceedings of 44th ACM/IEEE Design Automation Conference DAC 2007, pp. 396–399 (2007)Google Scholar
  22. 22.
    Keyes, R.W.: Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics 10(4), 245–247 (1975)Google Scholar
  23. 23.
    Oldiges, P., Lin, Q., Petrillo, K., Sanchez, M., Ieong, M., Hargrove, M.: Modeling line edge roughness effects in sub 100 nanometer gate length devices. In: Proceedings of Int. Conference Simulation of Semiconductor Processes and Devices, SISPAD 2000, pp. 131–134 (2000)Google Scholar
  24. 24.
    Pelgrom, M., Duinmaijer, A., Welbers, A.: Matching properties of MOS transistors 24(5), 1433–1439 (October 1989)Google Scholar

Copyright information

© International Association for Cryptologic Research 2013

Authors and Affiliations

  • Mudit Bhargava
    • 1
  • Ken Mai
    • 1
  1. 1.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityUSA

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