A Hardware Architecture for SIFT Candidate Keypoints Detection

  • Leonardo Chang
  • José Hernández-Palancar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5856)

Abstract

This paper proposes a parallel hardware architecture for the scale-space extrema detection part of the SIFT (Scale Invariant Feature Transform) method. The implementation of this architecture on a FPGA (Field Programmable Gate Array) and its reliability tests are also presented. The obtained features are very similar to Lowe’s. The system is able to detect scale-space extrema on a 320 ×240 image in 3 ms, what represents a speed up of 250x compared to a software version of the method.

Keywords

FPGA SIFT hardware architecture parallel SIFT 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Leonardo Chang
    • 1
  • José Hernández-Palancar
    • 1
  1. 1.Advanced Technologies Application CenterHavana CityCuba

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