FPGAs for High Accuracy Clock Synchronization over Ethernet Networks

  • Roland Höller
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The network interface node on one hand provides all necessary hardware support to be flexibly used in a broad range of applications. The switch add-on on the other hand accounts for the packet delay uncertainties of Ethernet switches and is crucial for high accuracy clock synchronization.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Roland Höller
    • 1
  1. 1.Institute of Computer Technology, ASIC DesignVienna University of TechnologyWiener NeustadtAustria

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