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Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing

  • Shigeyuki Takano
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

In order to improve the performance of reconfigurable computing, the number of reconfigurable units is increased with advance of semiconductor technology. The array of reconfigurable units can be configured to application-specific pipelined processing datapath. Then configuration overhead will be critical overhead of total execution time for dynamic reconfiguration based system. In this paper, models of efficient configuration methodology and application-specific pipelined stream processing are proposed. Adaptive processor architecture is also proposed, and discussed in summary.

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References

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    Wirthin, M.J., Hutchings, B.L.: DISC: The dynamic instruction set computer, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing. In: Proc. SPIE 2607, pp. 92–103 (1995)Google Scholar
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    Mattson, R.L., Gecsei, J., Slutz, D.R., Trainger, I.L.: Evaluation techniques for storage hierarchies. IBM Systems Journal 9(2), 78–117 (1970)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Shigeyuki Takano
    • 1
  1. 1.Graduate School of Computer Science and EngineeringUniversity of AizuAizu-Wakamatsu, Fukushima-kenJapan

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