Arbitrating Instructions in an ρμ-Coded CCM

  • Georgi Kuzmanov
  • Stamatis Vassiliadis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


In this paper, the design aspects of instruction arbitration in an ρμ-coded CCM are discussed. Software considerations, architectural solutions, implementation issues and functional testing of an ρμ-code arbiter are presented. A complete design of such an arbiter is proposed and its VHDL code is synthesized for the VirtexII Pro platform FPGA of Xilinx. The functionality of the unit is verified by simulations. A very low utilization of available reconfigurable resources is achieved after the design is synthesized. Simulations of an MPEG-4 case study suggest considerable performance speed-up in the range of 2,4-8,8 versus a pure software PowerPC implementation.


Link Register Core Processor Wait State Branch Instruction Architectural Solution 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Chang, H.-C., Chen, L.-G., Hsu, M.-Y., Chang, Y.-C.: Performance analysis and architecture evaluation of MPEG-4 video codec system. In: IEEE International Symposium on Circuits and Systems, May 28-31, vol. II, pp. 449–452 (2000)Google Scholar
  2. 2.
    Chang, H.-C., Wang, Y.-C., Hsu, M.-Y., Chen, L.-G.: Efficient algorithms and architectures for MPEG-4 object-based video coding. In: IEEE Workshop on Signal Processing Systems, October 11-13, pp. 13–22 (2000)Google Scholar
  3. 3.
    Kneip, J., Bauer, S., Vollmer, J., Schmale, B., Kuhn, P., Reissmann, M.: The MPEG-4 video coding standard - a VLSI point of view. In: IEEE Workshop on Signal Processing Systems(SIPS 1998), October 8-10, pp. 43–52 (1998)Google Scholar
  4. 4.
    Kuhn, P., Stechele, W.: Complexity analysis of the emerging MPEG-4 standard as a basis for VLSI implementation. In: SPIE Visual Comunications and Image Processing (VCIP), January 1998, vol. 3309, pp. 498–509 (1998)Google Scholar
  5. 5.
    Kuzmanov, G., Vassiliadis, S., van Eijndhoven, J.: A 2D Addressing Mode for Multimedia Applications. In: Deprettere, F., Teich, J., Vassiliadis, S. (eds.) SAMOS 2001. LNCS, vol. 2268, pp. 291–306. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  6. 6.
    Wazlowski, M., Agarwal, L., Lee, T., Smith, A., Lam, E., Silverman, H., Ghosh, S.: PRISM-II Compiler and Architecture. In: Proc. IEEE Workshop on FPGAs for Custom Computing Machines, April 5-7, pp. 9–16 (1993)Google Scholar
  7. 7.
    Hartenstein, R.W., Kress, R., Reining, H.: A new FPGA Architecture for Word-Oriented Datapaths. In: Hartenstein, R.W., Servit, M.Z. (eds.) FPL 1994. LNCS, vol. 849, pp. 144–155. Springer, Heidelberg (1994)CrossRefGoogle Scholar
  8. 8.
    Sima, M., Vassiliadis, S., Cotofana, S., van Eijndhoven, J.T., Vissers, K.: Field-Programmable Custom Computing Machines. A Taxonomy. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 79–88. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  9. 9.
    Vassiliadis, S., Hakkennes, E., Wong, J., Pechaneck, G.: The Sum Absolute Difference Motion Estimation Accelerator. In: Euromicro 1998, vol. 2 (August 1998)Google Scholar
  10. 10.
    Vassiliadis, S., Kuzmanov, G., Wong, S.: MPEG-4 and the New Multimedia Architectural Challenges. In: 15th SAER 2001, September 21-23 (2001)Google Scholar
  11. 11.
    Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN ρμ-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 275–285. Springer, Heidelberg (2001)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Georgi Kuzmanov
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering Lab, Electrical Engineering Dept.EEMCS, TU DelftThe Netherlands

Personalised recommendations