Fault Simulation Using Partially Reconfigurable Hardware

  • A. Parreira
  • J. P. Teixeira
  • A. Pantelimon
  • M. B. Santos
  • J. T. de Sousa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)


This paper presents a fault simulation algorithm and that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently leads to the minimal stuck-at fault list at the look-up-tables’ terminals. Fault injection is performed using local partial reconfiguration with small binary files. Our results on the ISCAS’89 sequential circuit benchmarks show that our methodology can be orders of magnitude faster than software or fully reconfigurable hardware fault simulation..


Field Programmable Gate Array Test Vector Fault Injection Fault Simulation Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • A. Parreira
    • 1
  • J. P. Teixeira
    • 1
  • A. Pantelimon
    • 1
  • M. B. Santos
    • 1
  • J. T. de Sousa
    • 1
  1. 1.IST / INESC-IDLisboaPortugal

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