Advertisement

Fault Simulation Using Partially Reconfigurable Hardware

  • A. Parreira
  • J. P. Teixeira
  • A. Pantelimon
  • M. B. Santos
  • J. T. de Sousa
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2778)

Abstract

This paper presents a fault simulation algorithm and that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently leads to the minimal stuck-at fault list at the look-up-tables’ terminals. Fault injection is performed using local partial reconfiguration with small binary files. Our results on the ISCAS’89 sequential circuit benchmarks show that our methodology can be orders of magnitude faster than software or fully reconfigurable hardware fault simulation..

Keywords

Field Programmable Gate Array Test Vector Fault Injection Fault Simulation Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Bushnel, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Kluwer Academic Pubs., Dordrecht (2000)Google Scholar
  2. 2.
    Niermann, T.M., Cheng, W.T., Patel, J.H.: PROFS: A fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Computer-Aided Design, 198–207 (1992)Google Scholar
  3. 3.
    Rudnick, E.M., Patel, J.H.: Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. In: Proc. of the IEEE International Test Conference (ITC), pp. 495-501 (1997)Google Scholar
  4. 4.
    Gonçalves, F.M., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Design and Test of Certifiable ASICs for Safety-critical Gas Burners Control. In: Proc. of the 7th. IEEE Int. On- Line Testing Workshop (IOLTW), July 2001, pp. 197–201 (2001)Google Scholar
  5. 5.
    Wieler, R.W., Zhang, Z., McLeod, R.D.: Simulating static and dynamic faults in BIST structures with a FPGA based emulator. In: Proc. of IEEE Int. Workshop of Field- Programmable Logic and Application, pp. 240-250 (1994)Google Scholar
  6. 6.
    Cheng, K., Huang, S., Dai, W.: Fault Emulation: A New Methodology for Fault Grading. IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems 18(10), 1487–1495 (1999)CrossRefGoogle Scholar
  7. 7.
    Hwang, S.-A., Hong, J.-H., Wu, C.-W.: Sequential Circuit Fault Simulation Using Logic Emulation. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems 17(8), 724–736 (1998)CrossRefGoogle Scholar
  8. 8.
    Civera, P., Macchiarulo, L., Rebaudengo, M., Reorda, M., Violante, M.: An FPGA-based approach for speeding-up Fault Injection campains on safety-critical circuits. IEEE Journal of Electronic Testing Theory and Applications 18(3), 261–271 (2002)CrossRefGoogle Scholar
  9. 9.
    Santos, M.B., Braga, J., Teixeira, I.M., Teixeira, J.P.: Dynamic Fault Injection Optimization for FPGA-Based Harware Fault Simulation. In: Proc. of the Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), April 2002, pp. 370–373 (2002)Google Scholar
  10. 10.
    Abramovici, M., Menon, P.: Fault Simulation on Reconfigurable Hardware. In: IEEE Symposium on FPGAs for Custom Computing Machines, pp. 182-190 (1997)Google Scholar
  11. 11.
    Abramovici, M., Menon, P.R., Miller, D.T.: Critical Path Tracing: An Alternative to Fault Simulation. In: IEEE Design Automation Conference, pp. 468 - 474 (1984)Google Scholar
  12. 12.
    Burgun, L., Reblewski, F., Fenelon, G., Barbier, J., Lepape, O.: Serial fault simulation. In: Proc. Design Auomation Conference, pp. 801-806 (1996)Google Scholar
  13. 13.
    Antoni, L., Leveugle, R., Fehér, B.: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 405-413 (October 2000)Google Scholar
  14. 14.
    Antoni, L., Leveugle, R., Fehér, B.: Using Run-Time Reconfiguration for Fault Injection Applications. In: IEEE Instrumentation and Measurement Technology Conference, May 2001, vol. 3, pp. 1773–1777 (2001)Google Scholar
  15. 15.
    Antoni, L., Leveugle, R., Fehér, B.: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 245–253 (2002)Google Scholar
  16. 16.
    Guccione, S., Levi, D., Sundararajan, P.: Jbits: A Java-based Interface for Reconfigurable Computing. In: Proc. of the 2nd Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), p. 27 (1999)Google Scholar
  17. 17.
    Lechner, E., Guccione, S.: The Java Environment for Reconfigurable Computing. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol. 1304, pp. 284–293. Springer, Heidelberg (1997)CrossRefGoogle Scholar
  18. 18.
    Sundararajan, P., Guccione, S., Levi, D.: XHWIF: A portable hardware interface for reconfigurable computing. In: Proc. of Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications, SPIE 4525, August 2001, pp. 97–102 (2001)Google Scholar
  19. 19.
    Brglez, F., Bryan, D., Kominski, K.: Combinational Profiles of Sequential Benchmark Circuits. In: Proc. Int. Symp. on Circuits and Systems (ISCAS), pp. 1229–1234 (1989)Google Scholar
  20. 20.
    Xilinx Inc., Virtex-E 1.8V Field Programmable Gate Arrays, Xilinx DS022 (2001)Google Scholar
  21. 21.
    Xilinx Inc., Virtex Series Configuration Architecture User Guide. Application Note: Virtex Series, XAPP151 (v1.5), September 27 (2000)Google Scholar
  22. 22.
    Cha, H., Rudnick, E., Patel, J., Iyer, R., Shoi, G.: A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Transactions on Computers 45(11), 1248–1256 (1996)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • A. Parreira
    • 1
  • J. P. Teixeira
    • 1
  • A. Pantelimon
    • 1
  • M. B. Santos
    • 1
  • J. T. de Sousa
    • 1
  1. 1.IST / INESC-IDLisboaPortugal

Personalised recommendations